Era COMPUTATRUM: February 2026

Saturday, February 28, 2026

FEB.(2nd Half) 2026

February 15, 2026

Speaking of which, due to soaring DRAM prices, there are concerns that computer-related manufacturers may struggle with earnings this year. I also saw an article saying that even boxed CPUs are no longer selling well on Amazon’s online store. It seems that DIY PC users are paying the price for data centers absorbing massive amounts of memory. GPU cards have finally started to return in terms of product variety, but minimum prices have risen.
A little while ago, I mentioned in a “mini update” that installing the January Windows Update — “2026-01 Security Patch (KB5074109) (26200.7623)” — could cause frame-rate drops on NVIDIA graphics cards. Apparently, applying KB5077181, which will be distributed in the February Windows Update, resolves the issue. It also includes fixes for other bugs, including—surprisingly—a “Notepad vulnerability.” I’ll just wait for it to roll out automatically.
The day before yesterday, I wrote that AWS’s CEO commented that the market and industry are overreacting to AI writing code. Supporting that view, there was an article noting that about ten years ago, when AWS captured a large share of the software market, similar “doomsday” narratives emerged—but in the end, no software companies went bankrupt because of it. Thinking back, there were many transitions: freeware during the PC-communication era, GPL (now generally called OSS) in the UNIX world, Linux being released for free, and later the rise of SaaS on the web. Despite all these shifts, the software industry has not disappeared.

February 16, 2026

By the way, the India AI Impact Summit is being held this week. According to an interview with Intel’s Vice President for the India region, India generates 20% of the world’s data but owns only 2% of global server capacity. In terms of data center power capacity, the figures are said to be: the United States at 53 GW, China at 20 GW, Europe at 13 GW, and India at 1.6 GW (with an additional 1.7 GW planned by 2027). There is clearly significant room for growth.
There was also a press release stating that AMD will deliver Helios systems to India. The scale is said to be 200 MW. Since one Helios rack reportedly consumes about 0.18 MW, even rounding to 0.2 MW suggests roughly 1,000 racks will be deployed. With 72 GPUs per rack, that would amount to 72,000 GPUs across 1,000 racks. These will be introduced as an AI platform by HyperVault AI Data Center Limited, a subsidiary of Tata Consultancy Services (TCS). I recall reading an article around mid-last month about AMD forming a partnership with TCS.

Another AMD-related item: SoftBank issued a press release stating that it has jointly developed with AMD an orchestrator for partitioned use of AMD GPUs. AMD Instinct GPUs already support partitioning features. A demonstration is planned at MWC in Barcelona next month. In a similar vein, I’ve heard of Fujitsu’s AI Computing Broker, which I believe provides a mechanism to partition NVIDIA GPUs. NVIDIA offers features such as MIG (Multi-Instance GPU) and vGPU. While partitioning can help address GPU shortages, it also seems like a necessary mechanism to increase utilization of GPU servers and accelerate return on investment.

February 17, 2026

At the India AI Impact Summit 2026, which began yesterday, Qualcomm reportedly exhibited a humanoid robot. Apparently, Qualcomm has a robotics and automotive division and is building a general-purpose robotics architecture covering not only humanoids but also everything from home-use robots to industrial autonomous mobile robots. I don’t recall seeing much coverage of Qualcomm beyond smartphones, PCs, and communications chips.

Another Qualcomm-related topic: because Qualcomm holds essential patents related to the 5G communications standard, smartphone manufacturers must obtain patent licenses from Qualcomm. Naturally, these are not free, and the license fees are added to smartphone prices as royalties. In the UK, there had been a class-action lawsuit alleging that Qualcomm unfairly charged royalties and raised smartphone prices. However, since the royalties are not unreasonable per se, the lawsuit has now reportedly been withdrawn. The royalty for a 5G device is said to be around $16.
Speaking of smartphones, there are reports that Arm, which provides CPU architectures, plans to establish an AI semiconductor research facility at its Austin, Texas site, with support from the Texas state government. Until recently, Arm’s business centered on selling Neoverse N/V architectures and related IP, but it has shifted toward selling CSS (Compute Subsystems). Last year, I believe Arm also announced that it would develop its own chips. Given that Cortex and other designs have long been manufactured at TSMC and Samsung, producing chips in-house should be feasible. As semiconductor manufacturing moves away from being smartphone-centric and toward HPC and AI as the main drivers, it will be interesting to see what kinds of chips Arm brings to market.
On the AI front, NVIDIA issued press releases regarding GB200 and GB300. Compared to Hopper-based platforms, the cost per one million tokens is reportedly reduced to one-tenth with GB200 NVL72 and to one-thirty-fifth with GB300 NVL72. Furthermore, GB300 NVL72 is said to achieve up to 50× throughput per megawatt. GB300 MVL is being adopted by Microsoft, CoreWeave, and OCI (Oracle). CoreWeave had already announced at the end of last month that it would adopt Vera Rubin. With Vera Rubin, compared to Blackwell, the cost per million tokens for MoE (Mixture of Experts) inference is said to be one-tenth, and throughput per megawatt is 10× higher.

Another AI-related development: Fujitsu announced an “AI-driven software development platform.” It is said to address three challenges: labor shortages, replacement of maintenance work, and moving away from the traditional man-month calculation model. Understanding the Japanese role of SE (system engineer) may be helpful here. By AI-automating practical tasks such as system construction, coding, and maintenance in response to customer IT department requirements, the expectation is that SEs—previously overwhelmed with routine work—will be able to spend more time in in-depth discussions with customers. The core AI is reportedly Takane, a Japanese-language LLM developed jointly by Fujitsu and Cohere. As I wrote a few days ago, it seems to be Fujitsu’s proprietary LLM created in collaboration with Cohere. Customer-created specifications often contain local terminology and implicit assumptions; from the description, it appears that the system is designed to handle such nuances effectively in Japanese. This may represent one concrete way AI is entering real-world practice, and it is worth watching how it develops

February 18, 2026

By the way, it appears that NVIDIA has sold all of its shares in Arm. If I recall correctly, the discussion about NVIDIA acquiring Arm dates back to around 2020. That acquisition ultimately failed, but since Arm was relisted on NASDAQ in 2023, this complete divestment means that Arm’s future stock price movements will no longer have any direct impact on NVIDIA.

I don’t think this means that Arm-architecture CPUs such as Grace or Vera will disappear, but given NVIDIA’s investment relationship with Intel, how things unfold from here is something to watch closely.

Another NVIDIA-related item: it seems NVIDIA has signed a GPU supply agreement with Meta. The deliveries will start with the current GB300, followed by Vera Rubin. Meta plans to deploy these in its multi-gigawatt AI factory “Prometheus” in 2026, and later in the 5-gigawatt AI factory “Hyperion” planned a few years down the road. In terms of GPU count, this would amount to several million units—almost impossible to visualize. Jensen Huang’s efforts at the end of January to coordinate Taiwan-wide production of GPU racks may well have been in preparation for this.

February 20, 2026 Time of Arm Server (topic.1)

Speaking of which, the partnership between NVIDIA and Meta that was reported the day before yesterday appears to be having a broader impact. With NVIDIA making a major move into the data center space, there are concerns about the implications for Intel and AMD. Meta is already reportedly NVIDIA’s second-largest customer by volume, and beyond adopting GB300 and Vera Rubin for AI workloads, Meta is also introducing Arm CPUs for its data centers—raising concerns about the impact on x86. NVIDIA’s move has multiple dimensions.

I’d like to go into a bit more detail, since I took a break from blogging yesterday.

One aspect is NVIDIA’s positioning as a data center supplier. NVIDIA has been calling this an “AI factory,” but in reality it looks very much like a full-scale mega data center. What started as DGX SuperPODs for AI training has expanded to include inference, driving down per-token costs to promote wider adoption. By supplying systems at the rack level and even offering standalone Arm CPUs, NVIDIA has effectively become a supplier of mega-scale AI data centers.

Looking at CPUs, Grace has 72 cores and Vera has 88 cores, both Arm CPUs. In the Arm world, AWS’s Graviton5 has 196 cores, but Vera supports two threads per core, yielding 172 threads. On the x86 side, Xeon 6E offers 144 cores per socket, with two sockets totaling 288 cores. In a superchip configuration, Vera reportedly mounts two superchips per tray; assuming a dual-socket configuration, this would amount to 344 threads. AMD’s Turin (Zen 5c) reaches 768 threads in a dual-socket setup, so there’s always something larger to compare against—but Vera appears competitive as a data center CPU for the current generation.

As for GPUs, in supercomputers, GPUs already outnumber CPUs. When IBM and NVIDIA built ORNL’s Summit in 2018, the ratio was two IBM POWER9 CPUs to six Volta GPUs. This trend continues not only with GB300 and Vera Rubin but also with AMD’s Helios, where GPU counts exceed CPU counts. Seen this way, AI data centers are becoming structurally similar to supercomputers.

Perhaps the most significant point is the server ecosystem shift. Fujitsu demonstrated that Arm CPUs could be used in supercomputers by integrating SVE into the A64FX used in Fugaku, which led to SVE2 being included starting with the Armv9 architecture. This boosted Arm’s presence as a server CPU beyond its traditional role in smartphones. While Arm-based PCs such as Apple’s M series and Qualcomm’s Elite have gained visibility, Arm servers using Fujitsu’s A64FX or Ampere Computing’s Altra Max and AmpereOne never achieved major market presence. NVIDIA’s move this time likely means that a vendor—NVIDIA—is supplying Arm CPUs in large volumes specifically for AI data centers. This is clearly different from merely selling architecture licenses.

Meta (formerly Facebook) founded the Open Compute Project (OCP), a standardization body for data center hardware, together with Google and Microsoft. HPE and Supermicro are suppliers of OCP-compliant servers. In October last year, Arm, NVIDIA, and AMD all joined OCP as board members. AMD’s Helios rack is also believed to be OCP-compliant. In this context, Meta’s purchase of Arm CPUs from NVIDIA is likely intended to build OCP-based servers.

That concludes the discussion on NVIDIA and Meta.
Below are several investment-related topics. The fate of NVIDIA’s previously rumored $100 billion investment in OpenAI had become unclear, but it now appears that NVIDIA is participating in OpenAI’s funding round with a $30 billion investment. This is reportedly unrelated to the earlier $100 billion figure. In South Korea, there is also a plan to introduce 260,000 NVIDIA GPUs by 2030, following 13,000 units last year and an additional 15,000 units this year.

With the India AI Impact Summit underway, NVIDIA has also announced investments in India. Data centers totaling 70 MW are reportedly under construction in Mumbai and Chennai, with NVIDIA systems expected to be deployed there. A few days ago, AMD announced a partnership with Tata Consultancy Services (TCS), and now OpenAI is also said to have partnered with TCS, starting with a 100 MW AI data center and eventually expanding to 1 GW. Beyond investments, Qualcomm—who exhibited a humanoid robot—has reportedly partnered with Tata Electronics on automotive semiconductor manufacturing, with an OSAT facility located in Assam.

While not an investment or partnership, there was also an article about Fujitsu CEO Takahito Tokita giving a speech. He reportedly stated that excessive reliance on AI for specialized skills is risky, and that AI should instead support richer ideas and creativity by facilitating communication between experts and non-experts, including general employees and customers. With this philosophy at its core, industries can grow further and create more jobs. NVIDIA’s Jensen Huang and AWS’s Matt Garman appear to be expressing similar views. It increasingly feels like a picture is emerging in which AI creates more work, rather than eliminating it.

There was also an article stating that AMD has become a guarantor for financing raised by Crusoe, a data center operator in Ohio. The loan is reportedly from Goldman Sachs, with AMD’s chips themselves used as collateral. Neither AMD nor Goldman Sachs has confirmed this.

Google is reportedly offering a $100 million investment to Fluidstack, a cloud computing startup, likely in search of deployment opportunities for its TPUs. While Anthropic has adopted TPUs, NVIDIA still dominates overall AI compute power, and Google appears eager to expand its influence. Perhaps we are moving from an era of “build and sell” to one of “invest and get others to use.”
Finally, we get to chips. There are reports that Ryzen CPUs based on AMD’s Zen 6 architecture may be delayed until 2027. Zen 6 is expected to use TSMC’s 2 nm process. Internal testing reportedly achieved 6.5 GHz operation, suggesting that 2 nm prototype chips already exist. Zen 6–based EPYC Venice is slated for use in Helios and already has manufacturing and shipping plans, so AMD is likely prioritizing that. On the consumer side, there are also concerns about severe memory shortages, making it unlikely that conditions will be ready for a Zen 6 Ryzen debut before at least 2026.

Another AMD-related note: the Radeon RX 9060 XT reportedly reached 4.769 GHz under enhanced cooling conditions, apparently setting a world record for GPU overclocking.
A brief software-related item: there was an article noting that Linux kernel 7.0 will remove the driver for Intel’s 440BX chipset. On a personal note, I believe the ASUS motherboard in the PC I built in 2000 used the 440BX. That brings back memories. The CPU was a Pentium III (Coppermine, 0.18 µm), and despite having no real software to use it with, I built it as a dual-CPU system. Even now, I’m not entirely sure what I wanted to do with it.
Open-PGL, hosted on GitHub and rumored to have been discontinued by Intel, is reportedly being archived by the Academy Software Foundation (ASWF). ASWF is one of the projects hosted by the Linux Foundation.

February 21, 2026 Human & AI Error (topic.2)

There are also rumors that Intel’s Nova Lake-S will launch in 2027. It had been expected in late 2026, but appears to slip into the following year. I just read an article yesterday suggesting that AMD’s Zen 6–based Ryzen would also arrive in 2027, and it seems Intel may be on a similar timeline. In AMD’s case, the delay is likely due to prioritizing Zen 6 EPYC, but for Nova Lake, it may be that Intel’s 18A production lines are fully booked. They are probably being used for Xeon 6+E Clearwater Forest or Xeon 7 Diamond Rapids, both aimed at data center or HPC markets. It does seem that the consumer market will face a tough environment this year.

Another Intel-related topic: there have reportedly been layoffs of around 6,000 people at Intel’s Oregon sites, raising some concerns about corporate stability. Among researchers, Oregon (OR) is well known as Intel’s U.S. R&D base—many Intel research papers list “Intel Corp., Hillsboro, OR.” Seeing layoffs even at such a core R&D site is rather disheartening.
Over the past couple of days, many articles have appeared claiming that AWS’s coding AI caused service outages. AWS’s code-generation AI tool, called Kiro, apparently also performs operational tasks. The outages reportedly occurred twice last December, but I don’t recall hearing about them at the time—apparently because they occurred in China. One outage lasted 13 hours, while the other was not visible to customers. The information seems to have come from an internal AWS leak, while the official explanation cites human error. From what I’ve read, Kiro chose to delete and rebuild systems and executed this without human intervention. The users operating Kiro had overly broad privileges, leading to widespread impact. Whether this was Kiro’s fault or the users’ fault is debatable, but there are a few troubling points: execution without human involvement, and referring to humans with broad administrative authority simply as “users.” These “users” may be Kiro users, but within AWS they are likely employees with operational responsibility.

Executing actions without human oversight is something that should not be done, in order to prevent irreversible accidents. This is not because it “blurs responsibility,” but because automation without proper fail-safe and foolproof mechanisms has long been recognized as dangerous—ever since the days of Thomas Edison. This lesson is written in blood in the history books. AI may be intelligent, but it does not bleed, so caution is essential. AWS also announced layoffs of 16,000 employees last month, with internal emails reportedly sent before the public announcement. The fact that such internal stories are leaking may be related to the wave of workforce reductions.

One more AWS-related item, finally a technical one: AWS has released the Hpc8a instance. Compared to the previous Hpc7a generation, memory bandwidth is reportedly improved by 42%. The CPU is listed as a 192-core AMD Zen 5–based EPYC, which likely means Zen 5c (Turin), manufactured on TSMC’s 3 nm process. Both Zen 5 and Zen 5c support two threads per core, but SMT is disabled here, resulting in 192 threads. In HPC workloads, where data is processed sequentially and synchronously, single-thread performance is critical and SMT is often less valued. In data centers, concerns such as noisy neighbors and security also make SMT less desirable. While SMT is effective for increasing throughput with fewer cores, it may no longer be essential in the era of many-core CPUs with strong single-thread performance.
Finally, a political topic. A U.S. court has ruled that the Trump-era tariffs are illegal. It remains to be seen how this will affect TSMC’s massive planned investments in the United States, but the ruling does not address whether already-paid tariffs will be refunded or how such refunds would be handled. There also appear to be multiple alternative legal bases for tariffs, so the situation may not change much. Moreover, if a presidential order is issued and approved by Congress, it would become law, which seems quite possible. There is little point in reacting emotionally either way. At a press conference, former President Trump reportedly suggested that Taiwan had “stolen” semiconductor technology. In the DRAM era of the 1980s, Japan would almost certainly have been named instead. I can’t help but feel a bit sorry for Taiwan.

February 22, 2026

There was an article stating that NVIDIA has partnered with Idaho National Laboratory (INL) in Idaho on the development of nuclear AI applications. NVIDIA’s technology is expected to be applied to the design, manufacturing, construction, and operation of reactors developed at INL. This appears to be part of the Genesis project and a component of U.S. energy policy. Since digital twin technology is mentioned, NVIDIA Omniverse will likely be used. One wonders whether AI training models for nuclear reactions inside reactors might eventually be developed and even released as open source—though concerns about nuclear weapons applications make that unlikely.

Another NVIDIA-related note: for several years now, there have been occasional reports of GPU power connectors melting or burning. Possibly in response, there was an article noting that some Dell PCs use screw-fastened connectors for GPU auxiliary power. This likely helps prevent fluctuations in contact resistance caused by cable movement. High-end desktops can require power supplies exceeding 1,000 W. When large currents flow, even small increases in contact resistance can cause significant voltage drops and substantial heat generation via Joule heating. For example, at 400 W and 12 V, about 33 A flows; if contact resistance increases by just 10 mΩ due to heating, voltage drops by 0.33 V. If sensors detect this and raise voltage to compensate, current increases further, causing even greater voltage drop—leading to a runaway process that can result in burning. The trigger is variation in resistance.
There was also an article about a Toronto-based startup called Taalas developing an AI chip named HC1, manufactured on TSMC’s 6 nm process. It hardwires the generative AI model Llama 3.1 8B and reportedly achieves 17,000 tokens per second (TPS)—a figure that made me do a double take. Just last week I wrote that Llama 3.1 70B achieved 2,100 TPS on Cerebras; although the parameter counts differ (8B vs. 70B), this is an order of magnitude higher. According to the company, HC1 is two orders of magnitude faster than Blackwell, with one-twentieth the token cost, and can be air-cooled. While it’s common knowledge that specialized hardware can deliver higher performance and lower power consumption, the hardwired nature means it cannot support other LLMs. I also wonder whether reinforcement learning is possible on this chip alone.

The company says that changing the LLM can be handled by modifying wiring layers, but this reportedly takes two months. The number of layers modified and their position in the stack matter: the finest masks are those for the transistors and the metal layers immediately above them, while upper layers follow “reverse scaling,” with wider pitch and lower mask costs. However, wider pitch reduces routing density, potentially requiring more layers and higher mask costs, and there are limits to how many layers can be added. The chip size is reportedly 815 mm²—about 28 mm × 29 mm—very close to the practical manufacturing limit. Moving to 3 nm would reduce size somewhat, but wafer costs would then come into play. Still, as an exploration of how much faster LLMs can be when hardwired, this is a very interesting approach. A hybrid system—hardwiring a core LLM and supplementing reinforcement learning with GPUs—could be compelling in terms of both performance and power efficiency.
SoftBank Group CEO Masayoshi Son has reportedly proposed the “Arizona AI Mega Project,” a plan to build an AI and robotics industrial park in Arizona. The R&D hub would include semiconductor manufacturing units, housing for engineers, and a smart grid—effectively a technology development city. If robotics is included, this could serve as a hub for physical AI. SoftBank participated in the Stargate Project last year and invested in OpenAI, and through its ownership of Arm, it has decided to develop processors in-house, acquiring Ampere Computing. This may indicate that SoftBank is beginning to solidify a concrete exit strategy.

February 23, 2026

By the way, it appears that Intel may be designing a unified core that integrates its P-cores and E-cores. More precisely, Intel is reportedly planning to hire project members for a unified-core initiative, and it is not entirely clear whether this means a full integration of P and E cores.
In the past, there was a project called “Royal Core,” reportedly conceived by Jim Keller (with a CPU codename that may have been “Beast Lake”), and that design was said not to have separated P-cores and E-cores.

In reality, the decision to split P and E cores in the 12th-generation Core i series (Alder Lake) may have been a strategy to reduce power consumption while remaining on the 10 nm node, by bringing in Atom-based single-thread cores. Alder Lake’s Intel 7 process was essentially an enhanced version of Intel’s 10 nm SuperFin technology. Since the minimum feature size remained the same, packing in more circuitry would naturally increase power consumption, which may have led Intel to adopt separate P-core and E-core architectures.

As I wrote the other day, once single-thread performance improves and core counts increase, SMT may become less important. Starting with the second generation of Core Ultra (Lunar Lake / Arrow Lake, manufactured on TSMC 3 nm), the Lion Cove P-core has already moved to single-thread operation. Assuming process scaling continues smoothly, it may indeed become feasible to unify P-cores and E-cores again.
Another Intel-related item: there are reports about Intel’s 3000 W power supply units for servers and data centers. With a 12 V output, that corresponds to 250 A. These units are water-cooled rather than air-cooled. GaN and SiC are used as power devices, and the units have obtained 80 PLUS Platinum certification. In data centers, cooling water lines would typically be integrated into the infrastructure, but for standalone servers, would they attach an AIO (All-in-One) radiator unit? It is an interesting detail to consider.
On a slightly different note, some quantum computing news: a contract for an IBM quantum computer to be delivered to the Campania region of Italy has reportedly been suspended. The issue does not appear to lie with IBM’s proposal itself, but rather with questions raised about the bidding process. There is a project underway to establish a “Quantum Valley” in southern Italy, and this suspension may delay its progress.

February 24, 2026

It seems AMD has also entered into a GPU supply partnership with Meta. Just last week, Meta finalized a GPU supply agreement with NVIDIA, and now it appears to be AMD’s turn. Meta is reportedly planning to install 6 GW worth of Helios rack systems equipped with AMD’s Instinct MI400-series GPUs. There is also information suggesting that these GPUs will be tuned specifically for Meta, raising speculation that they may be customized versions of the MI400.
The CPU is EPYC, based on Zen 6 Venice, with Zen 7 Verano also under consideration. Assuming one Helios rack consumes about 0.2 MW, 6 GW would correspond to 30,000 racks. With 72 GPUs per rack, that comes out to a simple calculation of roughly 2.16 million GPUs. At that volume, producing customized GPUs would still make economic sense. Naturally, this cannot be completed in a single year, so the deal appears to be a multi-year contract.
As with the OpenAI deal, this agreement also includes warrants for 160 million shares of AMD common stock. The mechanism seems to be that as Helios deployments progress, Meta receives AMD shares accordingly. Issuing all 160 million shares at once would dilute AMD’s stock, so the allocation is apparently staged. There are also conditions tied not only to GPU volume but to AMD’s stock price at each stage. As Meta purchases GPUs and AMD’s performance improves, corresponding shares are allocated. During the OpenAI deal, this structure was criticized as potentially circular trading. AMD’s aim is presumably to catch up to NVIDIA in terms of market capitalization—though at present AMD’s market cap is still less than 10% of NVIDIA’s.
Several more NVIDIA-related topics. There are renewed reports suggesting that NVIDIA may be preparing to enter the notebook PC market, with announcements of N1/N1X possibly imminent. The N1/N1X CPU+GPU itself is already on the market as GB10. Despite the name, the CPU appears to be a hybrid of Arm Cortex-X925 and Cortex-A725, rather than Grace. The C1 used in Grace was likely a successor to the X925. The GPU uses the Blackwell architecture, though its performance is presumably scaled down.
NVIDIA’s target seems to be the market for CPUs with integrated GPUs (iGPUs). Rumors of a launch in the first half of 2026 have not yet disappeared, although there was no announcement at CES in January. Whether anything will be announced at the March GTC is still unclear. In any case, the consumer market environment this year looks unfavorable.
Another NVIDIA item: the company has partnered with Singtel to promote AI adoption in Singapore. Singtel is the country’s major integrated telecom operator. Together, they have established an applied AI Center of Excellence for both public and private sectors. At last week’s India AI Impact Summit, although CEO Jensen Huang was absent, NVIDIA demonstrated efforts such as building a digital twin of Tata Motors’ automotive factory using the Omniverse platform and launching initiatives for robot learning with logistics companies. NVIDIA appears to be actively pushing physical AI in India.
Next, an NPU-related topic. Intel reportedly considered acquiring SambaNova but has since abandoned the plan. However, Intel did participate in part of SambaNova’s funding, so the relationship has settled into an investment partnership. The two companies will also engage in technical collaboration over multiple years. They are expected to build systems combining SambaNova’s SN50 chip with Xeon processors. Intel’s consumer CPUs already include NPUs derived from its acquisition of Movidius, but SambaNova’s technology seems likely to be paired primarily with Xeon.
Finally, a software-related topic. Anthropic reportedly published a blog claiming that its Claude Code can rapidly rewrite COBOL code, traditionally used on mainframes. Following this, IBM’s stock price reportedly dropped by around 13%. Rewriting COBOL has been discussed for decades, and IBM itself has long pursued initiatives to migrate COBOL systems to Java. There have been many such efforts in the past, but I don’t recall stock prices being affected before.

This time, Anthropic’s blog seems to have had an impact because the software industry itself has become highly sensitive to AI coding developments. It may not be entirely realistic, but if AI can just as easily rewrite code into COBOL as out of it, one could imagine a future less constrained by programming languages. Whether that is truly the case remains an open question.

February 25, 2026

By the way, Apple reportedly plans to manufacture the Mac mini in the United States. The company will open an Advanced Manufacturing Center in Houston, Texas, intended as a domestic production base for AI servers. “Sovereignty” has become a key buzzword recently. This facility is likely envisioned as a massive complex where manufacturing lines, data centers, Apple Intelligence, and human training all coexist.

Arizona, neighboring Texas, is home to TSMC’s Fab 21, which is expected to supply the semiconductors for the Mac mini. There are also reports that Apple has signed a contract for the supply of 100 million chips. Within Texas itself, Austin hosts key companies such as Arm, TI, and Broadcom.
Speaking of Arm, its recent quarterly results were strong, with particularly strong royalty revenue from the data center segment. AWS released Graviton 5 in December, and instances have since become available. It seems likely that Arm began charging AWS royalties for these chips around that time. If royalties are charged per core, Graviton 5’s 196 cores would represent a substantial amount per chip. NVIDIA’s Vera, by comparison, has two threads per core, with 88 cores and 176 threads. Whether royalties are based strictly on core count is an interesting question.

Another Arm-related topic: Arm has partnered with the Indonesian government on engineer education, aiming to train 15,000 chip design engineers. There was recently news that Qualcomm completed the design of a 2 nm Snapdragon chip in India, and it appears that chip design engineers are in short supply globally. Designing chips requires IP macros such as basic logic gates, arithmetic units like adders and multipliers, on-chip memories like caches, and controllers for DDR and PCIe interfaces. Shortages of engineers capable of designing such IP have been discussed for several years. By training engineers familiar with the Arm architecture and Arm’s IP, this initiative aims both to alleviate talent shortages and to generate foreign revenue.
ASML in the Netherlands has reportedly succeeded in boosting the power of EUV lithography light sources, increasing output from the current 600 W to 1,000 W. Market introduction is targeted around 2030, with 1,500 W and even 2,000 W also in view. It seems the industry is entering the kilowatt era. The impact on semiconductor manufacturing would be significant: wafer throughput is expected to rise from 220 wafers per hour to 330, a 50% increase.

The key question is where these systems will be deployed. Likely candidates include TSMC, Intel, Samsung (and GlobalFoundries), SK Hynix, and Japan’s Rapidus. EUV tools are now being installed in an increasing number of regions: Taiwan (TSMC), the U.S. (Arizona for TSMC; Arizona, Oregon, and Ohio for Intel; Texas for Samsung; New York for IBM and others), Ireland (Intel), Korea (Samsung and SK Hynix), Hokkaido (Rapidus), and eventually Kumamoto for TSMC. Strengthened light sources imply applicability to advanced nodes, making Taiwan and Ohio particularly realistic destinations—though this is, of course, speculation.

February 26, 2026

By the way, today (February 25 in the U.S.) NVIDIA announced its earnings. Both fourth-quarter and full-year results were released. Full-year revenue reportedly reached $215.9 billion, which translates to approximately ¥32.4 trillion at an exchange rate of 150 JPUSD. This represents 65% year-on-year growth. Fourth-quarter revenue alone was $68.1 billion, up 20% quarter-on-quarter and 70% year-on-year, exceeding the annual growth rate. This suggests particularly strong growth in the latter half of the fiscal year. With 91% of revenue coming from data centers, these numbers underscore NVIDIA’s central role in the recent AI semiconductor boom.
Despite these stellar results, NVIDIA’s stock price has not risen as much as one might expect. This does not necessarily mean there is no room for growth. Massive shipments of GB300 and Vera Rubin for data centers are planned, and while memory supply constraints exist, demand for RTX 6090 GPU cards remains, and N1/N1X products for notebooks are also waiting in the wings.

Investor concerns seem to revolve around two opposing risks: caution toward a potential AI bubble, and fears that AI might fundamentally disrupt the software industry. Investors are caught between the possibility that AI investment becomes circular trading that eventually collapses, and the possibility that AI succeeds too well and destroys existing software business models. In either case—whether AI is “real” or “fake”—pessimism currently prevails.

Recently, CEO Jensen Huang and AWS CEO Matt Garman have repeatedly stated that the software industry will not be destroyed and that the future is bright. Yet when news spread that Anthropic could rewrite COBOL, even IBM’s stock saw drops of 13% or even 27%. Some are even predicting the extinction of SaaS, coining the term “SaaS-pocalypse.” Leaders like ServiceNow CEO Bill McDermott and Salesforce CEO Marc Benioff have pushed back against this narrative. While customer support staffing has been reduced, AI agents have made SaaS more useful, and the number of companies using SaaS is reportedly increasing. Jensen Huang has also suggested that the market is wrong.

AI agents will leverage SaaS and other existing software to support more companies than before. Existing software will still be needed, as will staff who support businesses in new ways. Executives likely already see a model in which AI actually increases the amount of work. When stock prices begin to rise again, that may be the point at which markets accept this view and concerns about circular trading subside.
Another NVIDIA-related note: last month, the U.S. government reportedly approved exports of H200 GPUs to China, and Chinese companies appeared open to importing them. However, it seems that H200s have not yet entered China. The export approval is likely conditional, with strict security monitoring, and Chinese firms may be hesitant to proceed under such constraints.
One CPU-related topic: Broadcom has reportedly shipped Fujitsu CPUs. The product is described as a “3.5D Face-to-Face Computing SoC,” which appears to refer to Fujitsu’s FUJITSU-MONAKA CPU under development. Beyond Fujitsu’s own materials, overviews have also been presented at TSMC symposia and Arm events.

“3.5D” likely refers to a configuration where some chiplets mounted on a silicon interposer (commonly called 2.5D integration) use 3D stacked LSIs. The computing die is manufactured using TSMC’s 2 nm process, while the cache memory die uses a 5 nm process. These are bonded face-to-face, with the cache underneath. In addition, an I/O die (5 nm) is included. AMD’s 3D V-Cache also uses face-to-face bonding, but in AMD’s case the CCD is on the bottom and the cache on top.

It feels as though Fujitsu is now the only company continuing to develop CPUs in Japan. Its previous CPU, A64FX for the Fugaku supercomputer, included HBM, but this new chip targets data centers and does not include HBM. Mass production is expected to begin in the latter half of this year. Broadcom appears eager to deploy this 3.5D SoC technology across a variety of chips.

February 27, 2026

By the way, in OpenAI’s recent funding round, NVIDIA was said to be investing $30 billion, but it now appears that SoftBank invested $30 billion and Amazon invested $50 billion, bringing the total raised to $110 billion. NVIDIA’s contribution reportedly takes the form of 3 GW of dedicated inference capacity and 2 GW of training capacity.
Amazon’s participation seems like a new development. As a result, OpenAI has secured 2 GW of capacity on AWS using Trainium 3 and, in the future, Trainium 4. On the AWS side, Amazon is set to become OpenAI’s exclusive third-party cloud distribution provider. This apparently means that when OpenAI Frontier—the OpenAI subsidiary that operates AI agent services—offers those services, they will be provided exclusively through AWS (Amazon Bedrock). The 2 GW of Trainium capacity is likely allocated for this purpose.

Microsoft remains an existing shareholder of OpenAI and continues to collaborate with it, but OpenAI’s AI agent services will not be offered through Azure. Existing OpenAI services delivered via Azure will continue. This suggests a division of roles: stateful APIs such as AI agents on AWS, and stateless APIs on Azure.
Another AWS-related item: there was news that AWS plans to build a data center in Louisiana. The investment is reported to be around $12 billion, though the power capacity was not specified. Infrastructure development is underway, including a power supply network incorporating 200 MW of solar generation, as well as water systems for cooling. About 87% of the cooling reportedly relies on outside air. While water cooling is used, heat exchange through radiators normally relies on ambient air. Construction is expected to create around 1,500 jobs, with approximately 540 full-time positions for data center operations. Supercomputer construction has long been considered a form of public works, and it seems data center construction has now entered the same category.
Turning to NVIDIA-related topics, the ripple effects of NVIDIA’s earnings continue to spread. NVIDIA’s contribution to TSMC’s revenue is reportedly $23 billion, accounting for 19% of the total—up 7 percentage points from 12% in 2024. By contrast, Apple’s share of TSMC revenue is $20.5 billion (17%), down 5 points from 22% last year. As a result, Apple has ceded its position as TSMC’s largest customer to NVIDIA. It had been said during TSMC’s earnings call last month that NVIDIA had overtaken Apple, but these figures make it clear.
A supercomputer using NVIDIA GPUs at Eli Lilly has reportedly gone into operation. Called “LillyPOD,” it is a DGX SuperPOD equipped with 1,016 Blackwell GPUs, construction of which began in October 2024. It is said to be the most powerful system in the pharmaceutical industry. With 72 GPUs per rack, 1,016 GPUs would amount to 14 racks plus 8 GPUs. Since each computing tray contains four GPUs, that leaves an extra two trays’ worth of GPUs—presumably installed somewhere.
Regarding Meta: after announcing that it would receive several million GPUs from NVIDIA, and then—just two days before NVIDIA’s earnings announcement—declaring that it would also receive 6 GW worth of GPUs from AMD, Meta has now reportedly announced that it will procure TPUs from Google as well. This may be a form of diversification.
Next, some AMD-related items. AMD CEO Lisa Su reportedly stated that the data center market will reach $1 trillion by 2030. According to Japan’s Ministry of Internal Affairs and Communications, the market size in 2024 was $416.1 billion. Reaching $1 trillion by 2030 would require annual growth of roughly 16%. There is no doubt that data centers are a growth industry. Terms like “mega data centers” and “hyperscalers” were already in use around 2020, but the wave of AI adoption has dramatically accelerated investment.
As I mentioned briefly during the India AI Impact Summit two weeks ago, current data center capacity by region is approximately 53 GW in the U.S., 20 GW in China, 13 GW in Europe, and 1.6 GW in India. Japan stood at 1.37 GW as of 2024.

AMD has also partnered with Nutanix. The deal includes a $150 million investment from AMD and technical collaboration, with $100 million allocated specifically for joint technical initiatives. Nutanix provides services that enable hybrid clouds spanning private and public cloud environments. This partnership is likely aimed at delivering a full-stack solution—including AI—on the private cloud side. Nutanix had previously supported NVIDIA GPUs, and with this partnership, AMD GPUs will now also be supported. From a confidentiality perspective, many companies avoid storing sensitive information on public clouds like AWS. It seems we are entering an era in which AI agents will also be deployed in private clouds. That said, Nutanix reportedly lowered its earnings outlook due to constraints in CPU and memory supply.
AMD also announced Sorano, a Zen 5–based processor in the 8xx5 series. It is the successor to Siena, with core counts increased from 64 to 84. It is not yet clear whether it uses Zen 5 or Zen 5c. If it is Zen 5, it would require twelve 7-core CCDs (with one core disabled per CCD). If Zen 5c, it would require six 14-core CCDs (with two cores disabled each). Using twelve Zen 5 CCDs would physically resemble the 96-core-class EPYC 96x5 configuration. If the processor is to fit into the smaller SP6 socket rather than SP5, a configuration using six Zen 5c CCDs seems more realistic—but that remains speculative.
One Intel-related item: a senior vice president at Intel Foundry has reportedly moved to Qualcomm. Just last month, it seemed that an engineer who had long led GPU development at Qualcomm moved to Intel. Such exchanges of personnel are not uncommon.
Finally, two political topics. Anthropic and the U.S. Department of Defense—commonly known as the Pentagon, whose current formal designation translates roughly as the Ministry of War—appear to be in some dispute over an AI usage contract. The Department of Defense reportedly wants unrestricted use of Anthropic’s Claude AI for any lawful purpose. The contract value is said to be $200 million, and Anthropic is reportedly hesitant.

DeepSeek is preparing to release its next v4 model, but NVIDIA and AMD have reportedly been excluded from the GPU vendors’ early access list. Chinese domestic vendors such as Huawei are said to be given priority for several weeks. This appears to be a move to reduce dependence on the U.S. and protect domestic vendors.

February 28, 2026 From GPU to NPU (topic.2)

There are reports regarding AMD’s Zen 7 “Grimlock Ridge.” Although this is a desktop CPU, its CCDs are expected to be used in EPYC as well. Zen 6 has not yet reached the market but uses TSMC’s 2 nm process, while Zen 7 is expected to use the A14 (1.4 nm) process. The CCD is said to have 16 cores with an area of 98 mm². This 16-core CCD is reportedly codenamed “Silverton.” Separately, there appears to be an 8-core CCD called “Silverking,” with an area of 56 mm². For reference, Zen 6 CCDs have 12 cores and an area of 76 mm².
According to TSMC materials, the density improvement from N2 (2 nm) to A14 is about 1.2×, implying an area reduction to roughly 83%. While moving from 2 nm to 1.4 nm represents a full-node generational shift, it does not result in halving the area for the same core count as in earlier eras. Keeping 12 cores would yield an area of roughly 63 mm² (76 × 0.83). A 24-core CCD would be around 124 mm², slightly larger than previous CCDs. It appears AMD may have opted for two variants: a 16-core die (1.5× the core count) and a smaller 8-core die at roughly half that size. Powers of two like 16 and 8 may also be more convenient from a design standpoint.
The article also mentioned APUs. In Grimlock Point/Halo, CCDs are reportedly stacked on top of the I/O die. In Zen 5’s Strix Point and Zen 6’s Medusa Point (not yet released), CCDs and I/O dies are connected using FOEB (Fan-Out Embedded Bridge). Moving to a 3D structure dramatically shortens wiring distances, improving both latency and power efficiency. Incidentally, Zen 6–based EPYC Venice also uses FOEB, and its appearance differs slightly from Zen 5–based Turin and earlier packages.
Regarding yesterday’s OpenAI funding round, it appears that the 3 GW of inference-only capacity provided by NVIDIA as part of its $30 billion investment will be based on Groq, with which NVIDIA partnered last year. The partnership with Groq is reportedly a non-exclusive licensing agreement, but NVIDIA has hired Groq’s founder and built an internal development team. The extent of internalization is unclear, but announcements are expected at GTC in March.
Groq’s LPU is expected to use 3D stacking with cache memory, and LPUs will be rack-mounted and connected using NVLink Fusion. The GPU used is reportedly “Feynman,” manufactured on TSMC’s A16 process using BSPD (backside power delivery), which TSMC refers to as Super Rail. Groq refers to its processor as an LPU—Language Processing Unit—adding yet another letter to the expanding “XPU” family.

NVIDIA has reportedly begun shipping samples of Vera Rubin, with full-scale shipments expected in the second half of 2026. This is just a personal impression, but both NVIDIA and AMD seem to be rushing GPU sales. It appears there is a growing expectation that as various NPUs like Groq’s emerge and CPU+NPU configurations become the mainstay for low-power inference, GPUs may no longer be indispensable.

With sufficiently trained AI models, systems may not necessarily require GPU-heavy configurations. For companies that do not perform reinforcement learning frequently, the need for GPUs may be intermittent. In such cases, GPU+CPU deployments could become cost-disadvantageous.
Personally, I find it hard to justify buying a high-end GPU costing several hundred thousand yen just for occasional reinforcement learning. Without a clear path to monetization, it is not an attractive investment. (That said, business models already exist—and will likely grow—in which companies offer reinforcement learning as a service.) GPUs will still be needed for supercomputing applications such as drug discovery and weather prediction, so demand will not disappear. However, the explosive growth in AI semiconductor demand since last year, and the massive multi-gigawatt data center contracts being signed over multi-year periods, may reflect an anticipation that a future dominated by inference will eventually lead to saturation in training demand. From that perspective, it is not unreasonable to think that vendors feel compelled to sell GPUs aggressively now.
Finally, some TSMC-related topics. TSMC’s 2 nm process capacity is reportedly fully booked for the next two years. Mass production began late last year. Publicly announced 2 nm users include AMD’s Zen 6 CCDs and Fujitsu’s FUJITSU-MONAKA computing die, both of which are likely already coming off the line. Ongoing production likely includes Apple silicon, and NVIDIA has announced plans to use 2 nm for Rubin Ultra. MediaTek is also expected to develop products on 2 nm.

Regarding fabs, TSMC reportedly plans to build a new 2 nm manufacturing site in Tainan. Procedures are expected to be completed within 2026, with production targeted to begin in 2028.

There was also news about TSMC’s withdrawal from the GaN business. TSMC announced last summer that it would exit the GaN foundry business for power devices by July 2027. After withdrawal, Rohm—TSMC’s partner in the GaN business—is expected to take over. Gallium is a semiconductor material known for quite some time and is considered one of the rare metals.

One more TSMC-related note, or rather Taiwan-related: reports say that the U.S. government, via the CIA, has warned U.S. tech companies about the risk of a Chinese invasion of Taiwan by 2027. There seems to be a growing number of articles expressing concern about the concentration of semiconductor supply in Taiwan. The February 24 edition of The New York Times reportedly ran a feature on risks surrounding Taiwan.

This Blog text was translated by AI from Japanese Source Blog.

Saturday, February 14, 2026

FEB.(1st Half) 2026

February 1, 2026

So, February has begun. January felt fairly dense in terms of content. This month, we have ISSCC coming up.

Since the end of last month, NVIDIA CEO Jensen Huang has been visiting Taiwan. According to an article reporting on media interviews, when asked about AI-focused ASICs (in other words, NPUs), he expressed the view that their production volumes would probably never exceed those of GPUs. Even amid the AI semiconductor boom, it is hard to deny that GPUs remain dominant for now. Manufacturing will naturally prioritize GPUs as well. If, ten years from now, semiconductor fabs have doubled in number, it might be worth revisiting today’s remarks.
The keyword I mentioned yesterday, 800V HVDC (high-voltage direct current), is said to improve power efficiency by about 4.5% and reduce copper wiring usage by more than 60%. My understanding is that this applies to internal power distribution within AI factories. I’m a circuit designer rather than a power engineer, so I don’t claim deep expertise here.
NVIDIA has also published a blog post about renewing the National Quantum Initiative (NQI). This appears to be related to the U.S. government’s Genesis program and advocates the concept of quantum GPU supercomputing. NVIDIA has been working on quantum computing for some time, and I recall CUDA-Q being introduced at GTC. With the introduction of NVQ-Link last year, it seems that an environment has emerged that bridges quantum and classical computing, including physical interconnects. In terms of timing, following the first phase of NQI, the second phase was reportedly approved in December 2025, so this renewal looks like a move toward the next stage. Fujitsu, which announced collaboration with NVIDIA last October, is also heavily investing in quantum computing and is building a dedicated quantum computing facility at its Kawasaki plant. Incidentally, Kawasaki City also hosts an IBM quantum computer closer to the waterfront.
There was also an article claiming that as many as 18,000 engineers from Taiwan may be heading to TSMC’s U.S. fabs within this year. Currently, around 2,000 engineers of Taiwanese origin are working at the Arizona fab, but since operations began, local hiring has progressed and the number of engineers sent from Taiwan has reportedly decreased, making such a large number unnecessary. That said, with around six fabs planned, it is possible that roughly 10,000 people could relocate to the U.S. over the next decade. Samsung, meanwhile, is reportedly sending even more people—around 7,000—and is currently building a 2nm fab. As mentioned somewhere last month, TSMC follows an “N-2 rule,” meaning that 2nm production in the U.S. is still some way off. Samsung appears to be planning to move ahead first. It’s a bold strategy, but the enormous capital investment required for EUV makes it far from easy.

February 2, 2026

Last month, there was an article suggesting that Apple might manufacture the base M-series chips at Intel. More recently, however, another article argued that producing iPhone chips at Intel would be difficult. The reasoning given was Intel’s adoption of BSPDN (backside power delivery networks) in its 18A and 14A processes. Speculating about the failure mechanism, BSPDN requires thinner silicon, and smartphones also have very thin internal heat spreaders. As a result, heat generated by transistors may not spread laterally and would have to dissipate vertically, making it difficult to eliminate hotspots in compute units. This suggests that some form of thermal-aware power routing to enable lateral heat spreading might be necessary for BSPDN. (Traditionally, thermal vias have been used to conduct heat vertically.)
I had vaguely assumed that NPUs were mainly developed for in-house cloud use, but that may have been a misconception. AWS’s Trainium2 and Google’s TPU are reportedly being purchased in large volumes by Anthropic. AWS has disclosed in investor briefings that Trainium sales amount to several billion dollars, while Broadcom, which develops the ASICs for TPUs, has said TPU-related revenue reaches tens of billions of dollars. Of course, NVIDIA is reportedly approaching $200 billion in AI chip revenue, so even capturing 1% of the overall market could still be substantial. AI demand is clearly sustaining the market size, but if barriers to entry fall too much, the situation could turn into a bubble, so caution is warranted. At present, chip manufacturing capacity is the main bottleneck, keeping entry barriers high. The pace at which TSMC continues to build fabs will be crucial, and it seems TSMC is deliberately planning capacity with this in mind.
A few days ago I mentioned that NVIDIA uses SOCAMM in its Vera Rubin superchip, and it appears that Qualcomm and AMD will also adopt SOCAMM for AI chips. These LPDDR-based DRAM modules can be attached and detached later, which is extremely helpful in today’s environment of memory shortages, since memory packaging can be decoupled from chip packaging.

One more NVIDIA-related topic: while there have been a series of articles recently suggesting that NVIDIA’s $100 billion investment in OpenAI has not been going well, another article reports Jensen Huang saying that NVIDIA will make the largest investment in history. Details are still unclear, but guessing wildly, could this involve donating AI factories, similar to the first-generation DGX SuperPod? Perhaps the effort to solidify the supply chain in Taiwan and prepare for mass production of VR200 racks is connected to this.

February 3, 2026

At an Intel Japan event, it seems Intel announced the adoption of a new type of memory for AI PCs. The new memory is called ZAM (Z-Angle Memory), developed by PsyMemory, a SoftBank subsidiary. It appears to be a joint development involving SoftBank, the University of Tokyo, and Intel, with Fujitsu and RIKEN joining since last December. I read several articles, but the technical details were not entirely clear. To increase capacity, memory chips are stacked, but simple planar stacking traps heat in the center, degrading performance, increasing leakage, shortening lifespan, and reducing reliability. ZAM seems to address this issue.
Speculating freely, if chips were arranged vertically rather than stacked flat, heat could dissipate upward, since silicon has higher thermal conductivity than the insulating materials in wiring layers. Of course, this is an obvious idea, so perhaps the real innovation lies in solving the secondary challenges that arise. For example, a memory chip’s base likely contains SerDes I/O terminals—does this mean SerDes circuits are placed along the edge of vertically oriented chips? Or is there a separate SerDes chip (similar to a PHY in HBM) on which vertically oriented memory chips are arranged? In that case, edge terminal density would be extremely high. These kinds of thoughts make for endless technical speculation.
It was also reported that the founder of Nuvia, which Qualcomm acquired in 2021, is retiring. Nuvia held an Arm architecture license, and Qualcomm designed chips (Snapdragon with Oryon cores) under that license. Arm sued Qualcomm for license violations when Qualcomm attempted to manufacture and sell those chips, but a September 2025 ruling favored Qualcomm.

February 4, 2026

I believe today was AMD’s earnings announcement. NVIDIA exports performance-restricted GPUs to China, and AMD reportedly offers a China-specific GPU called MI308. This chip appears to comply with policies under the Biden administration and is likely based on the previous generation (MI300-based, CDNA3). Orders were reportedly received early in 2025, with shipments in Q4 2025. The next GPU approved for export to China is said to be the MI325 (also likely MI300-based).
Amid ongoing concerns about memory shortages, AMD reportedly expects the PC market to shrink. For enterprise customers, AMD plans to re-release Zen 3–based products that can be upgraded using DDR4. This likely refers to the EPYC 7003 Milan series, with CCDs manufactured on TSMC’s 7nm process and IODs on GlobalFoundries’ 14nm process. Perhaps AMD will redesign the IOD to refresh the memory subsystem, though that remains to be seen.

In addition, AMD disclosed that the Helios racks announced at CES 2026 are expected to be shipped to OpenAI. An agreement was reportedly reached last October to deliver a total of 6 GW, with about 1 GW planned for delivery in the second half of this year. It’s not entirely clear what it means to deliver products measured in power units.
Intel CEO Lip-Bu Tan reportedly announced at the Cisco AI Summit that Intel will intensify its focus on GPUs going forward. It will be interesting to see how Intel restarts its data center GPU efforts following NVIDIA and AMD. Reports last month about a Qualcomm GPU architect joining Intel now seem to fit into this narrative. A roadmap beyond Jaguar Shores may be revealed before long.
At an event hosted in Houston, Texas, by France-based Dassault Systèmes, NVIDIA CEO Jensen Huang appeared as a guest speaker and announced a partnership with Dassault. Dassault’s parent company has roots in the defense industry, if I recall correctly. The collaboration aims to build an industrial AI platform supporting digital twins for industrial use. According to articles, Huang spoke for about 40 minutes during a 90-minute session, highlighting his popularity. I can understand why.

February 5, 2026

While watching the midday news, I saw a report that TSMC will build a 3nm production line at its Kumamoto fab (FAB23). Since 2nm entered mass production at the end of last year, the N-2 rule would normally make 4nm the most advanced process deployed overseas, so this feels like an exceptional move. Since last year, expansion work at JASM in Kumamoto has reportedly stalled, and there had been speculation that the second fab would be 6nm or 4nm—or even 2nm. Given that Rapidus is building a 2nm line in Hokkaido, having 2nm in Kumamoto as well would have been problematic. Settling on 3nm seems like a reasonable compromise.
Incidentally, a “3nm process” does not mean a 3nm wiring width. That was roughly true for older nodes like 28nm or 16nm, but from 7nm onward, the number is essentially a branding term. Looking it up again recently, the 3nm node corresponds to G48M24, and 2nm to G48M22. That suggests a gate length of around 12nm. I plan to explain what GxxMxx means sometime over the weekend.
Yesterday saw AMD’s Q4 and full-year earnings, and today brought Qualcomm’s Q1 and Arm’s Q3 results. Many articles note that all three companies’ stock prices fell after earnings announcements. The common reason appears to be concerns that memory shortages will cloud future performance outlooks. Since none of these companies are memory manufacturers, this suggests that memory shortages have become a shared challenge across the entire industry this year.

February 6, 2026

It appears that Intel and AMD have informed customers that shipments of CPUs to China will be delayed. Intel’s lead time is reportedly about six months, while AMD’s is expected to be up to ten weeks (approximately 2.5 months). The Intel CPUs in question are Xeon 4 (Sapphire Rapids) and Xeon 5 (Emerald Rapids), and the article reports that a large backlog of purchase orders has accumulated. Both Xeon 4 and Xeon 5 are manufactured on Intel 7.
There is also an article suggesting that NVIDIA may not release a gaming-oriented RTX-50 SUPER this year. It was reportedly planned to be announced at CES 2026, but the announcement has been postponed to December. The reason given is a potential shortage of LPDDR7. There is also speculation that the market launch of Rubin-based RTX-6000 series products may be delayed.
Another piece of NVIDIA-related news is that the location of its Taiwan headquarters land appears to have been decided in Taipei City.
Demand for AI semiconductors has led to a shortage of memory, with the impact spreading to CPUs and GPUs. There are forecasts suggesting that in 2026, data centers will absorb as much as 70% of total memory supply. Some articles note that if all three—memory, CPUs, and GPUs—are in short supply, servers themselves will become the subject of fierce competition. Traditionally, there has been a large gap between the pace of improvement in memory transfer speeds and CPU data processing speeds, a phenomenon known as the “memory wall.” If, however, the gap between market demand and semiconductor supply causes performance across the entire computer-related industry to decline, this might be considered a different kind of “memory wall.”
Mini news: A Windows 11 security patch reportedly reduces the frame rate of NVIDIA GeForce GPUs.

January 2026 Security Patch (KB5074109) (26200.7623)

February 7, 2026

It seems MediaTek has also released its earnings results. In its forward outlook, the company reportedly reached an agreement with TSMC to adopt both the 2nm and A14 (1.4nm) process nodes. While 2nm has already entered mass production, A14 was announced around last spring at TSMC’s Technology Symposium. Adopting leading-edge processes suggests that MediaTek intends to aggressively enter the HPC market. It is believed that memory shortages will mainly pressure the low-end market, while the high-end market will be less affected.
As an alternative to CoWoS, panel-based packaging technologies for mounting multiple chips within a package are beginning to emerge. TSMC refers to replacing CoWoS wafers with panels as CoPoS, while companies other than TSMC—such as ASE, SPIL, and SEMCO—are reportedly working on FOPLP (Fan-Out Panel-Level Packaging), which replaces wafers in FOWLP with panels. This appears to be an attempt to challenge CoWoS (and TSMC).
Speaking of packaging, TSMC has announced plans to build a 3nm production line in Kumamoto, Japan, but how packaging will be handled may be a challenge. There is reportedly a TSMC 3DIC R&D center in Tsukuba, but it does not seem intended for mass production. The TSMC Arizona fab is expected to add packaging facilities in the future. Rapidus has stated that it plans to handle packaging in-house as well (I recall seeing its president promoting a 600mm panel on television). Even if 3nm wafers are produced in Kumamoto, will they need to be shipped back to Taiwan? This may be an issue going forward.
In a somewhat unusual story, an article reported that an AMD Ryzen Threadripper Pro 9995WX reached 5.325GHz via overclocking with a custom water-cooled heatsink, consuming 1300W. The Ryzen 9995WX is based on Zen 5 (TSMC 4nm). The CPU was likely delidded and attached directly to the die. The water block design was reportedly unconventional, using S-shaped channels in the vertical plane rather than straight grooves, extending the flow path and improving cooling efficiency.
There was also an article suggesting that Qualcomm may use a cooling technology called Heat Pass Block (HPB) in the next Snapdragon generation. Details are unclear, but it may be applied to 2nm-generation chips. Another report states that Qualcomm’s India team has completed tape-out of a 2nm chip, though neither the chip details nor the specific fab were disclosed. If it is a Snapdragon, some speculate it may be taped out on Samsung’s 2nm process, but this remains uncertain.
Finally, an AWS topic: In its quarterly earnings, AWS reportedly announced plans to invest $200 billion in AI. Alphabet and Microsoft have also recently declared large AI investments. The total AI-related investment across these companies appears to be increasing year by year. Separately, several articles reported on intrusions into AWS environments using AI. Due to lax user-side security, environments were reportedly compromised in as little as eight minutes. Because AI does not hesitate to engage in trial-and-error like humans, once inside, lateral movement is said to be very fast.

Another AWS item: AWS and German power company RWE (Rheinisch-Westfälisches Elektrizitätswerk) reportedly signed a contract for the supply of 110MW of offshore wind power. AWS will provide cloud services to RWE, and RWE will supply electricity to AWS. A related article notes that Europe’s aging power transmission grid is slowing the deployment of high-voltage lines, delaying data center construction—by about two years compared to other regions. Google and Meta are reportedly facing similar issues. Even when discussing sovereign data centers or sovereign AI, whether facilities are actually located domestically makes a major difference. Accelerating grid upgrades appears necessary.

February 8, 2026 "Process Node" Status Quo (topic.2)

There was an article revealing internal details about NVIDIA’s $100 billion investment in OpenAI not going well. One background factor appears to be that OpenAI’s internally developed code-generation assistant (Codex) has underperformed, requiring inference capabilities beyond what NVIDIA GPUs alone can provide. As a result, OpenAI may be renting systems from companies such as Cerebras. Groq has also been mentioned as a candidate, and it is speculated that NVIDIA’s acquisition of Groq may be related to this situation. Since OpenAI is exploring multiple inference engines (possibly including AMD’s), this may be unappealing to NVIDIA. According to the article, this may be the real reason the investment is not proceeding smoothly.
Another NVIDIA-related note: NVIDIA reportedly allows its internal engineers to use a customized version of Anysphere Inc.’s code-generation AI, Cursor. The amount of generated code reportedly tripled, but since the bug rate did not improve with the initial deployment, NVIDIA customized the tool.

One more NVIDIA item: Samsung is reportedly set to begin mass production of HBM4 for Vera Rubin later this month.
Homework submission follows.

A few days ago, I wrote that “a 3-nm production line will be built at TSMC’s Kumamoto fab (FAB23), but ‘3 nm’ does not refer to the minimum circuit linewidth; since the 7-nm generation, the node name has effectively become just a trademark.” I would like to explain what this “minimum circuit linewidth” used to mean, and why today the numbers no longer match physical reality. To do that, it is first necessary to explain what “minimum circuit linewidth” actually signifies.

In semiconductor manufacturing, photomasks and exposure tools are used to fabricate LSIs by essentially making a reduced copy of a circuit pattern. When we make reduced photocopies in everyday life, if we reduce them too much, the characters blur and become unreadable. In the same way, in semiconductor fabrication, excessive scaling causes circuit formation to fail. Through various technical innovations, engineers push scaling to the very limit at which the circuit still functions without failure. The smallest wiring width that can be realized at this limit is what is called the minimum circuit linewidth.

Now, how do we shrink this minimum linewidth? When we hear about magnification or reduction, we might think of lenses, but in the semiconductor world the history is really about shortening the wavelength of the light source used in lithography tools. In process nodes such as 0.25 μm in the 1990s or 90 nm in the 2000s, light sources with wavelengths of 248 nm (KrF lasers) or 193 nm (ArF lasers) were used. From the 65-nm generation onward, 193-nm laser light was passed through water (ArF immersion), effectively achieving an equivalent wavelength of about 134 nm. A natural question is how it is possible to create patterns finer than the wavelength itself. This is achieved through optical correction techniques applied when printing wiring patterns. Even photomasks that look unintelligible at first glance can, when illuminated with monochromatic laser light, produce the intended wiring dimensions. To further increase wiring density, techniques such as multiple patterning—using several masks for the same layer—have been adopted, making photomask design CAD tools extremely complex.

With this historical background, from the 65-nm generation through the 16-nm, 14-nm, and 10-nm generations, process nodes (≈ minimum circuit linewidths) advanced using the same 134-nm-equivalent light source. This corresponds to the period when Intel manufactured Skylake (2015) on its 14-nm process, and when TSMC produced the iPhone X (2017) using its 10-nm process. After that, Intel struggled with its 10-nm process and did not produce Ice Lake until 2019. It is fair to say that this period marked the practical limit of ArF immersion lithography. TSMC, meanwhile, moved to the 7-nm generation and began introducing EUV lithography. EUV uses a wavelength of 13.5 nm—an order of magnitude shorter. (Terms such as “generation,” “process,” and “node” appear frequently here; note that they are used with roughly the same meaning.)

At this point some speculation is involved, but EUV has relatively low throughput, which likely made techniques such as multiple patterning difficult to use. That, in turn, would make it harder to form patterns much finer than the wavelength or to dramatically increase wiring density. From here on, the meaning of “scaling” the minimum circuit linewidth (≈ process node) begins to change.

By the 10-nm and 7-nm generations, both Intel and TSMC had transitioned to FinFETs, also known as tri-gate structures. In planar transistors before FinFETs, increasing transistor width (and thus drive current) required elongating the gate laterally, increasing area. With FinFETs, however, width can be gained in the vertical direction by increasing fin height, allowing the occupied area to be reduced. It is like moving from single-story houses to apartment buildings: the same number of households can live on a smaller plot of land. If the spacing between fins can also be reduced, area savings become even greater—like densely packed apartment complexes. The same applies to gate-all-around (GAA) FETs, such as TSMC’s nanosheet transistors at 2 nm and beyond, or Intel’s RibbonFETs at 18A and beyond.

Advancing a semiconductor process node carries several expectations, the most important being that LSIs become smaller. For the same circuit, a smaller area means more chips per wafer and therefore lower cost. Alternatively, for the same die area, more circuitry can be integrated, yielding higher performance at the same cost. Consequently, even if the minimum circuit linewidth itself does not shrink, advancing the process node still makes sense as long as more circuitry can be packed in. In this way, starting with the FinFET + EUV generations, the minimum circuit linewidth has effectively remained unchanged while the process node name has continued to advance as a branding concept.

So how can we tell the minimum circuit linewidth for each process node? Semiconductor manufacturers generally refer to industry roadmaps as benchmarks, though there is no strict obligation to follow them. About ten years ago, this roadmap was called the ITRS; today it is known as the IRDS. The IRDS covers the entire semiconductor industry, and within it the lithography section presents roadmaps for transistor structures and minimum circuit linewidths.

In the lithography roadmap, there are two definitions related to minimum linewidth. One is the minimum pitch of simple wiring—the distance from the center of one wire to the next, including the gap in between. Since wiring is metal, this is denoted as Mxx. The other is the contacted gate pitch, which represents transistor density. This pitch is defined as the distance between the centers of adjacent gates, including the source/drain contact next to the gate. More precisely, it is gate–space–contact–space–gate, measured from gate center to gate center. Because it is a gate pitch, it is denoted as Gxx. The GxxMxx notation I mentioned a few days ago comes directly from these roadmap values.

For reference, in the 2024 edition of the lithography roadmap, the values are G48M24 for the 3-nm node in 2024, G48M22 for the 2-nm node in 2025, and G48M22 again for the 1.4-nm node in 2027. Since this is a roadmap, these are projections and should be treated as such. Interpreting the numbers as explained above, G48 means the combined value of gate + space + contact + space. Dividing by four gives approximately 12 nm each for the gate, spaces, and contact. Similarly, M22 represents wire + space, so dividing by two yields about 11 nm each for the wire and the space. Considering that the EUV wavelength is 13.5 nm, it is reasonable to think that both gate and wiring minimum widths are on the order of about 12 nm.

According to the roadmap trend, from the 3-nm node to the 2-nm node, the gate pitch (G) remains unchanged while the metal pitch (M) shrinks by 2 nm. From the 2-nm node to the 1.4-nm node, both G and M are unchanged. There is no definitive proof that TSMC or Intel strictly adhere to these values, but they are reasonable reference dimensions. While more circuitry does fit as process nodes advance, the pace is no longer such that each generation doubles transistor count, as in the classic interpretation of Moore’s law. When people say that Moore’s law has slowed down, they are referring to exactly this situation.

In conclusion, to reiterate, advancing the process node today increases circuit density through means other than shrinking the minimum circuit linewidth. While this poses no industrial problem, the “xx-nm generation” indicated by the process node has diverged from the actual minimum wiring width. As an aside, the lattice constant of silicon is 5.431 angstroms. A “14A” process node literally means 14 angstroms, and future roadmaps go below 10A to 7A and 5A. Demand for AI semiconductors is pushing nodes forward, and with transistor structures evolving toward CFETs, scaling efficiency is expected to improve. If, when we reach the 5A node, someone says, “Isn’t something strange here?”, I hope this explanation will come to mind.

That was a long explanation, but that is all I wanted to convey. I think it is a wonderful development that a 3-nm-generation manufacturing line will be built at TSMC’s Kumamoto fab.

February 9, 2026

It seems TSMC held a board meeting in Kumamoto, likely related to the 3nm line construction. After Chairman C.C. Wei reportedly made a request to Japan’s prime minister, the board may have approved it. If so, holding the meeting in Kumamoto makes sense. Incidentally, TSMC held a board meeting in Arizona last year.
Two Intel-related topics have emerged. One concerns chipset information for the next-generation Intel Core Ultra Series 4 (Nova Lake). The 9xx series chipsets begin with Z/B/Q/W, with Z990 as the high end. These are expected to reach the market around the Christmas shopping season this year.
The other is that Intel’s “Intel On Demand” service has reportedly ended unofficially (with no formal announcement). Intel CPU spec sheets list many features, but users must pay separately to enable some of them. Initially this was called SDSi (Software Defined Silicon). This includes SGX (Software Guard Extensions), which provides device-rooted information protection. “In Device We Trust” will likely grow in importance, and it remains to be seen whether such features will be enabled by default in future CPUs.
In data center news, Murata Manufacturing reportedly used 5th-generation AMD EPYC processors to triple simulation throughput while reducing workload power consumption to one-third. These were likely Zen 5 (Turin, 4nm) CPUs. Zen 5c (3nm) has smaller memory capacity and may be less suitable for simulations. While the baseline system is unclear, lower voltage, more cores, and larger cache typically reduce power and increase throughput—an example of scaling benefits.
Numerous articles report that AWS partnered with STMicroelectronics. ST will supply microcontrollers and communication chips for AWS data centers and is also co-developing chips with AWS.
Another data center note: MC Digital Realty’s NRT14 data center in Inzai (Chiba Prefecture) reportedly became the first in Japan to receive NVIDIA certification for liquid-cooled DGX systems, enabling GB200 NVL72 racks. “NRT” is derived from Narita Airport’s IATA code.

February 10, 2026

There are reports that MediaTek may adopt Intel’s 14A process. Other articles recently noted access to TSMC’s 2nm and A14. Since “A14” and “14A” sound similar—and “14A” could also be read as angstroms—confusion is possible.
Related to Intel’s 14A, backside power delivery (BSPD) is reportedly set to become standard from 18A onward. TSMC is expected to offer it as an option, possibly from N2P or A16. BSPD faces several challenges. One is self-heating: thinning the silicon layer increases thermal resistance, making it harder for heat to dissipate from both signal (front) and power (back) sides, causing junction temperatures to rise. Backside power routing will require simultaneous electrical and thermal design. The necessary simulation tools likely already exist; what remains is execution.
Another challenge lies in LSI design methodology. With separated signal and power layers, new design and verification environments are needed. Signal routing cannot simply be tightened due to crosstalk concerns, and timing analysis, designer intuition, and reuse from previous generations make technology migration difficult. This may be the larger issue. TSMC works closely with EDA vendors such as Synopsys, Cadence, and Siemens—how Intel handles this is less clear. Rapidus in Japan has stated it will support BSPD relatively early.

Another Intel note: The upcoming desktop CPU Nova Lake-S may reach a maximum power consumption of 700W when all 52 cores are fully active. Not long ago, that was the power rating of an entire mid-tower PC.
In a less common area, Cisco released the Silicon One G300 network chip, manufactured on TSMC’s 3nm process, competing with Broadcom’s Tomahawk. Network paths often become bottlenecks in AI computing, and rerouting can improve performance. Silicon One G300 reportedly improves some AI workloads by 28%.
ARM Holdings’ recent earnings showed strong royalty income due to AI-driven chip sales, though licensing revenue was lower than expected. Licensing fees are paid during chip development, while royalties are paid after chip sales. While memory shortages may reduce chip sales in 2026, licensing revenue provides some offset.
In cloud news, Google reported an astonishing 48% growth in Q4. While Google’s revenue base is smaller than Microsoft’s or AWS’s, 48% represents roughly 1.5× growth, likely driven by Gemini 3. AWS reportedly surpassed Microsoft in Q4 revenue. Cloud business remains strong overall.

February 11, 2026

It appears that MediaTek has won the ASIC development contract for Google’s TPU v8e. Up through TPU v7p, Broadcom handled the work, although MediaTek reportedly took charge of the I/O portion for v7p. This time, it seems MediaTek may have been awarded the entire design. An article suggests that SerDes performance was the deciding factor. For AI chips, communication bandwidth appears to be critical.
Continuing with Google-related news, there was an article stating that Intel and Google jointly validated Intel TDX (Trust Domain Extension), identified vulnerabilities and bugs, and implemented countermeasures. TDX was introduced after SGX, and while both are security-related features, SGX operates at the application level, whereas TDX provides security at the VM level. Trust in the device itself (root of trust) is becoming increasingly important. AMD has SEV, and Arm has CCA. Cloud service providers (CSPs) such as Google and Microsoft (Azure) provide a device-rooted chain of trust.
Another Intel-related topic: Toward the end of January, there was speculation that Intel Foundry would be used for the I/O chip of NVIDIA’s next-generation GPU, Feynman. New articles suggest that Intel may also be used for packaging. TSMC will still be involved, with an estimated split of roughly 75% TSMC and 25% Intel.
Continuing with NVIDIA news, I wrote last week that NVIDIA’s Taiwan headquarters was likely to be located in Taipei. It now appears that the contract has been officially signed. The lease term is 50 years, with an option to extend by up to 20 years. Starting from 2026, this would run as long as 2096.
Switching topics, regarding so-called “Trump tariffs” in Taiwan: In the semiconductor sector, it has been reported that U.S. suppliers designated by TSMC will be exempt from import tariffs. In other words, hyperscalers such as Google, AWS, and Microsoft will purchase large volumes of chips from TSMC, and if TSMC designates them as exempt vendors, U.S. tariffs on imports from Taiwan will be waived. This is reportedly based on legislation allowing Taiwanese semiconductor companies that have already invested in U.S. facilities to import chips duty-free up to 1.5 times their investment amount, or up to 2.5 times for new investments. Semiconductor companies can choose which customers receive the exemption. TSMC has made massive investments in the U.S. and plans to build around six fabs, and this appears to have paid off.
Finally, some news from Japan. There was an article stating that Fujitsu will begin domestic manufacturing of AI servers. The factory is reportedly located in Ishikawa Prefecture, likely operated by Fujitsu IT Products. Neither company has released a formal press announcement yet. Fujitsu’s server products, as well as the K and Fugaku supercomputers, were manufactured there. The stated goal is to prevent information leakage, suggesting the importance of domestic production. However, it is not entirely clear what is meant by “AI servers.” Are these IA (x86) servers, or could they be servers based on FUJITSU-MONAKA (TSMC 2nm), which Fujitsu is currently developing as a data-center CPU? Further details are awaited.
Mini news: In Windows 11’s semiannual update cycle, the upcoming release believed to be 26H1 will reportedly support only Arm CPUs and will not be an update to 25H2.

February 12, 2026

It appears that the NPU 6 integrated into Intel’s Nova Lake will deliver 74 TOPS of performance. By comparison, Panther Lake’s NPU 5 offers 50 TOPS, making Nova Lake about 1.5× faster. NPU 4, used in Lunar Lake, delivers 48 TOPS, while NPU 3 in Arrow Lake provides about 13 TOPS. Panther Lake was announced at CES in January, but it appears there will be no desktop version. Lunar Lake is also notebook-only, so for the first half of 2026, a refreshed Arrow Lake is expected for desktops, reportedly still with a 13 TOPS NPU. With Nova Lake arriving toward year-end, the NPU performance gap will be about 5.7×. Since Windows + Copilot is said to require 40 TOPS, those considering an AI PC may want to think carefully before choosing Arrow Lake Refresh. (NPU 4 and NPU 5 reportedly have similar performance, but differ in area efficiency.)
Another Intel-related item: Tower Semiconductor of Israel had planned to manufacture silicon photonics devices at Intel’s Fab 11X in New Mexico, but this plan has reportedly been canceled. Instead, Tower Semiconductor will carry out production in Japan, at a facility in Toyama (TPSCo Fab 7). Silicon photonics is expected to see growing demand for AI data centers.
Samsung has reportedly begun mass shipments of HBM4, marking its first deliveries to NVIDIA. SK hynix shipped samples earlier, but mass production shipments have not yet begun.
Another Samsung note: The next-generation smartphone CPU, Exynos 2600 (Samsung 2nm), will reportedly support Arm’s SME2. The competing Qualcomm Snapdragon 8 Elite Gen 5 is believed to support SME.
NVIDIA’s RTX 6000 PRO GPU is equipped with 96GB of GDDR7, but in China there is reportedly an RTX 6000D variant with 84GB. Since each GDDR7 chip is 3GB, this corresponds to 32 chips versus 28 chips. The 6000D also reportedly has a narrower bus and fewer shaders. Both are based on the Blackwell architecture. While it was unclear whether China imported the previous-generation H200, the fact that current Blackwell-based products are already available may be because they use GDDR rather than HBM. In other words, NVIDIA may have designed these products from the outset to be exportable to China.
Turning to AMD: According to a research firm, AMD’s revenue share in the overall server market exceeded 40% in Q4 2025, reaching 41.3%. It was 39.5% in Q3, so this may have been only a matter of time. AMD’s server CPU unit share stands at 28.8%, nearly 30%. In the desktop segment, AMD’s revenue share reached 42.6%, also exceeding 40%, with a CPU unit share of 36.4%. In both servers and desktops, AMD now accounts for roughly 40% of industry revenue.
In Japan-related news, Rapidus is reportedly planning monthly wafer production of 6,000 wafers in 2027, increasing to 25,000 wafers per month in 2028, and eventually to 60,000 wafers per month. Since 2026 is the year when 2nm-generation products enter the market, this seems to mark the real start. After 40nm, the number of fabs steadily declined, but at 2nm, Rapidus has joined TSMC, Intel, and Samsung. At the same time, AI semiconductor demand is surging, suggesting favorable conditions.
Regarding Fujitsu’s domestic server manufacturing mentioned yesterday, a press release now appears to have been issued, and domestic coverage has increased. The article I saw yesterday was from Nikkei Asia, so it may have been early. The “AI servers” turn out to be both servers based on FUJITSU-MONAKA and GPU servers using NVIDIA B300 and RTX 6000 PRO. FUJITSU-MONAKA adopts the Arm architecture, like Fugaku’s A64FX (TSMC 7nm).

February 13, 2026

I recall reading an article in mid-January that OpenAI had adopted Cerebras’s WSE, and now there is news that OpenAI has built its Codex model (GPT-5.3-Codex-Spark) on Cerebras. This is reportedly the first OpenAI model to run on non-NVIDIA hardware. Code generation speed is said to be 1,000 tokens per second (TPS). For comparison, Anthropic’s Claude Opus 4.6 was listed at 68.2 TPS. Other examples of models running on Cerebras include Meta’s Llama 3.1 70B at 2,100 TPS and OpenAI’s gpt-oss-120B at 3,000 TPS. Judging by these numbers, Codex may be a relatively heavy model, while at the same time highlighting the impressive capability of Cerebras. As a wafer-scale engine (WSE), it reinforces the idea that, for AI chips, size is performance.
There has been attention on comments by AWS CEO Matt Garman regarding the impact of generative AI on the software industry. Concerns have been raised that powerful code generation could make software development companies unnecessary or signal the end of SaaS, and SaaS-related stocks such as Salesforce have reportedly been weak. Posts on X also suggest that software houses are being cornered. Garman’s remarks appear to argue that these fears are exaggerated. At a recent Cisco AI Summit, NVIDIA’s Jensen Huang also stated that the outlook for the software industry is bright. The industry may currently be in a somewhat hysterical state. While generative AI may indeed encourage a shift from SaaS to in-house (on-prem) development and more personal coding, it is hard to imagine cloud services declining. Rather, as a platform, the cloud is likely to continue expanding alongside global population growth, and demand for software development is probably just getting started. When PCs emerged in the 1980s, there was talk of a “software crisis,” yet software engineers have remained in short supply ever since, partly because programming languages are difficult. It may be more accurate to say that the true value of software development expertise is only now coming into its own.
Another AWS-related item: There was an article stating that AWS will lead the construction of a data center in Washington State. It is reportedly located near a port and has a power contract with a nuclear plant. Although unconfirmed, it may be near a submarine cable landing point.
A bit of LSI-related news: I recall an article late last month suggesting that Apple’s base M5 might be manufactured by Intel, and now there are reports that the M5 Pro and Max may adopt TSMC’s SoIC packaging technology, separating CPU and GPU into chiplets. Recently, even large GPUs have begun separating I/O into chiplets, and most XPUs may now be chiplet-based. The article cited Qualcomm’s Snapdragon X2 Elite as an example that has not yet adopted chiplets.
A somewhat unusual topic: Japan’s PayPay is reportedly planning to list on Nasdaq in New York. It is said to be preparing for an IPO. Preparations began last year, but delays due to government shutdowns caused by budget shortfalls reportedly pushed the timeline to now. The ticker symbol will be PAYP.

February 14, 2026 Break the Curse of Software (topic.2)

It appears that Intel has discontinued Intel Quantum Passes, which were included in the Intel Quantum SDK. I do not fully understand the details, but originally, quantum programs would be compiled and executed on quantum chips such as Tunnel Falls. When using quantum simulators based on HPC systems or GPUs instead of actual quantum computers, programs must be compiled specifically for those simulators. Quantum Passes seem to have served as a bridge between quantum compilation and simulator-specific compilation. Intel has developed a quantum chip called Tunnel Falls and has provided it to research institutions; I recall reading an article in mid-January about its delivery to Argonne National Laboratory. Recently, Intel On Demand (formerly SDSi), which allowed users to purchase additional CPU features, appears to have been unofficially discontinued, and Intel’s open-source initiatives seem to be winding down.
Intel’s 52-core Nova Lake-S is rumored to reach 700W when power limits are removed. The core configuration is reportedly 16 P-cores (Coyote Cove, Intel 18A) with 16 threads, 32 E-cores with 32 threads, and 4 LP-E cores with 4 threads—all single-threaded per core. Up through the first-generation Core Ultra (Meteor Lake), P-cores supported two threads (Redwood Cove, Intel 4), but from the second generation onward, P-cores are single-threaded.
Yesterday I wrote that OpenAI achieved 1,000 TPS by running Codex on Cerebras’s WSE-3. A throughput of 1,000 TPS is said to correspond to human-level pair-programming responsiveness. Extending this idea, if AI can drive coding, could development timelines for software stacks—compilers, drivers, OS integration, databases, VMs, and porting existing applications—be shortened by analyzing processor architecture specifications? In other words, while it takes months to fabricate an LSI, if the architecture specification and RTL netlist exist as a “paper machine,” could at least a prototype software stack be ready by the time the chip arrives? Of course, it is not that simple, but today both CPUs and GPUs have relatively few architectural variants. If AI coding becomes widespread, it may influence processor design itself. Intel has tried several times to abandon x86 but was ultimately pulled back by its software legacy. Japan’s supercomputers moved from SPARC64 in the K system to Arm in Fugaku partly to broaden the software ecosystem. Perhaps AI coding will one day free architectures from software constraints—this thought occurred to me.
There was also an article about the launch of the Trusted Tech Alliance (TTA) at the Munich Security Conference, involving 15 companies from 10 countries. The founding members include Anthropic, AWS, Cohere, Ericsson, Google Cloud, Microsoft, Nokia, NTT, Rapidus, SAP, and six others, spanning AI, cloud, communications, semiconductors, and databases—the core industries of today’s digital society. The alliance aims to expand gradually. In a digital society where information spreads instantly worldwide, there are many benefits, but attackers can also strike from safe havens. For those without malicious intent, trust becomes essential for connectivity.
A bit more Japan-related news: NTT Data, a subsidiary of NTT and a TTA member, has reportedly signed a multi-year contract with AWS and acquired Dubai-based Zero&One, an AWS-certified partner. In another item, Fujitsu is set to give presentations and exhibitions at the India AI Impact Summit 2026, to be held next week. This is the event where many articles reported that NVIDIA’s Jensen Huang would be absent. Fujitsu will reportedly showcase quantum computing, FUJITSU-MONAKA, and demonstrations of its Japanese-language LLM, Takane. Takane is also being co-developed with Cohere, another TTA member.
ISSCC 2026 begins tomorrow. The plenary session on the 16th will feature four talks from MediaTek, IBM, Cadence, and Apple.