Era COMPUTATRUM: FEB.(1st Half) 2026

February 1, 2026

So, February has begun. January felt fairly dense in terms of content. This month, we have ISSCC coming up.

Since the end of last month, NVIDIA CEO Jensen Huang has been visiting Taiwan. According to an article reporting on media interviews, when asked about AI-focused ASICs (in other words, NPUs), he expressed the view that their production volumes would probably never exceed those of GPUs. Even amid the AI semiconductor boom, it is hard to deny that GPUs remain dominant for now. Manufacturing will naturally prioritize GPUs as well. If, ten years from now, semiconductor fabs have doubled in number, it might be worth revisiting today’s remarks.
The keyword I mentioned yesterday, 800V HVDC (high-voltage direct current), is said to improve power efficiency by about 4.5% and reduce copper wiring usage by more than 60%. My understanding is that this applies to internal power distribution within AI factories. I’m a circuit designer rather than a power engineer, so I don’t claim deep expertise here.
NVIDIA has also published a blog post about renewing the National Quantum Initiative (NQI). This appears to be related to the U.S. government’s Genesis program and advocates the concept of quantum GPU supercomputing. NVIDIA has been working on quantum computing for some time, and I recall CUDA-Q being introduced at GTC. With the introduction of NVQ-Link last year, it seems that an environment has emerged that bridges quantum and classical computing, including physical interconnects. In terms of timing, following the first phase of NQI, the second phase was reportedly approved in December 2025, so this renewal looks like a move toward the next stage. Fujitsu, which announced collaboration with NVIDIA last October, is also heavily investing in quantum computing and is building a dedicated quantum computing facility at its Kawasaki plant. Incidentally, Kawasaki City also hosts an IBM quantum computer closer to the waterfront.
There was also an article claiming that as many as 18,000 engineers from Taiwan may be heading to TSMC’s U.S. fabs within this year. Currently, around 2,000 engineers of Taiwanese origin are working at the Arizona fab, but since operations began, local hiring has progressed and the number of engineers sent from Taiwan has reportedly decreased, making such a large number unnecessary. That said, with around six fabs planned, it is possible that roughly 10,000 people could relocate to the U.S. over the next decade. Samsung, meanwhile, is reportedly sending even more people—around 7,000—and is currently building a 2nm fab. As mentioned somewhere last month, TSMC follows an “N-2 rule,” meaning that 2nm production in the U.S. is still some way off. Samsung appears to be planning to move ahead first. It’s a bold strategy, but the enormous capital investment required for EUV makes it far from easy.

February 2, 2026

Last month, there was an article suggesting that Apple might manufacture the base M-series chips at Intel. More recently, however, another article argued that producing iPhone chips at Intel would be difficult. The reasoning given was Intel’s adoption of BSPDN (backside power delivery networks) in its 18A and 14A processes. Speculating about the failure mechanism, BSPDN requires thinner silicon, and smartphones also have very thin internal heat spreaders. As a result, heat generated by transistors may not spread laterally and would have to dissipate vertically, making it difficult to eliminate hotspots in compute units. This suggests that some form of thermal-aware power routing to enable lateral heat spreading might be necessary for BSPDN. (Traditionally, thermal vias have been used to conduct heat vertically.)
I had vaguely assumed that NPUs were mainly developed for in-house cloud use, but that may have been a misconception. AWS’s Trainium2 and Google’s TPU are reportedly being purchased in large volumes by Anthropic. AWS has disclosed in investor briefings that Trainium sales amount to several billion dollars, while Broadcom, which develops the ASICs for TPUs, has said TPU-related revenue reaches tens of billions of dollars. Of course, NVIDIA is reportedly approaching $200 billion in AI chip revenue, so even capturing 1% of the overall market could still be substantial. AI demand is clearly sustaining the market size, but if barriers to entry fall too much, the situation could turn into a bubble, so caution is warranted. At present, chip manufacturing capacity is the main bottleneck, keeping entry barriers high. The pace at which TSMC continues to build fabs will be crucial, and it seems TSMC is deliberately planning capacity with this in mind.
A few days ago I mentioned that NVIDIA uses SOCAMM in its Vera Rubin superchip, and it appears that Qualcomm and AMD will also adopt SOCAMM for AI chips. These LPDDR-based DRAM modules can be attached and detached later, which is extremely helpful in today’s environment of memory shortages, since memory packaging can be decoupled from chip packaging.

One more NVIDIA-related topic: while there have been a series of articles recently suggesting that NVIDIA’s $100 billion investment in OpenAI has not been going well, another article reports Jensen Huang saying that NVIDIA will make the largest investment in history. Details are still unclear, but guessing wildly, could this involve donating AI factories, similar to the first-generation DGX SuperPod? Perhaps the effort to solidify the supply chain in Taiwan and prepare for mass production of VR200 racks is connected to this.

February 3, 2026

At an Intel Japan event, it seems Intel announced the adoption of a new type of memory for AI PCs. The new memory is called ZAM (Z-Angle Memory), developed by PsyMemory, a SoftBank subsidiary. It appears to be a joint development involving SoftBank, the University of Tokyo, and Intel, with Fujitsu and RIKEN joining since last December. I read several articles, but the technical details were not entirely clear. To increase capacity, memory chips are stacked, but simple planar stacking traps heat in the center, degrading performance, increasing leakage, shortening lifespan, and reducing reliability. ZAM seems to address this issue.
Speculating freely, if chips were arranged vertically rather than stacked flat, heat could dissipate upward, since silicon has higher thermal conductivity than the insulating materials in wiring layers. Of course, this is an obvious idea, so perhaps the real innovation lies in solving the secondary challenges that arise. For example, a memory chip’s base likely contains SerDes I/O terminals—does this mean SerDes circuits are placed along the edge of vertically oriented chips? Or is there a separate SerDes chip (similar to a PHY in HBM) on which vertically oriented memory chips are arranged? In that case, edge terminal density would be extremely high. These kinds of thoughts make for endless technical speculation.
It was also reported that the founder of Nuvia, which Qualcomm acquired in 2021, is retiring. Nuvia held an Arm architecture license, and Qualcomm designed chips (Snapdragon with Oryon cores) under that license. Arm sued Qualcomm for license violations when Qualcomm attempted to manufacture and sell those chips, but a September 2025 ruling favored Qualcomm.

February 4, 2026

I believe today was AMD’s earnings announcement. NVIDIA exports performance-restricted GPUs to China, and AMD reportedly offers a China-specific GPU called MI308. This chip appears to comply with policies under the Biden administration and is likely based on the previous generation (MI300-based, CDNA3). Orders were reportedly received early in 2025, with shipments in Q4 2025. The next GPU approved for export to China is said to be the MI325 (also likely MI300-based).
Amid ongoing concerns about memory shortages, AMD reportedly expects the PC market to shrink. For enterprise customers, AMD plans to re-release Zen 3–based products that can be upgraded using DDR4. This likely refers to the EPYC 7003 Milan series, with CCDs manufactured on TSMC’s 7nm process and IODs on GlobalFoundries’ 14nm process. Perhaps AMD will redesign the IOD to refresh the memory subsystem, though that remains to be seen.

In addition, AMD disclosed that the Helios racks announced at CES 2026 are expected to be shipped to OpenAI. An agreement was reportedly reached last October to deliver a total of 6 GW, with about 1 GW planned for delivery in the second half of this year. It’s not entirely clear what it means to deliver products measured in power units.
Intel CEO Lip-Bu Tan reportedly announced at the Cisco AI Summit that Intel will intensify its focus on GPUs going forward. It will be interesting to see how Intel restarts its data center GPU efforts following NVIDIA and AMD. Reports last month about a Qualcomm GPU architect joining Intel now seem to fit into this narrative. A roadmap beyond Jaguar Shores may be revealed before long.
At an event hosted in Houston, Texas, by France-based Dassault Systèmes, NVIDIA CEO Jensen Huang appeared as a guest speaker and announced a partnership with Dassault. Dassault’s parent company has roots in the defense industry, if I recall correctly. The collaboration aims to build an industrial AI platform supporting digital twins for industrial use. According to articles, Huang spoke for about 40 minutes during a 90-minute session, highlighting his popularity. I can understand why.

February 5, 2026

While watching the midday news, I saw a report that TSMC will build a 3nm production line at its Kumamoto fab (FAB23). Since 2nm entered mass production at the end of last year, the N-2 rule would normally make 4nm the most advanced process deployed overseas, so this feels like an exceptional move. Since last year, expansion work at JASM in Kumamoto has reportedly stalled, and there had been speculation that the second fab would be 6nm or 4nm—or even 2nm. Given that Rapidus is building a 2nm line in Hokkaido, having 2nm in Kumamoto as well would have been problematic. Settling on 3nm seems like a reasonable compromise.
Incidentally, a “3nm process” does not mean a 3nm wiring width. That was roughly true for older nodes like 28nm or 16nm, but from 7nm onward, the number is essentially a branding term. Looking it up again recently, the 3nm node corresponds to G48M24, and 2nm to G48M22. That suggests a gate length of around 12nm. I plan to explain what GxxMxx means sometime over the weekend.
Yesterday saw AMD’s Q4 and full-year earnings, and today brought Qualcomm’s Q1 and Arm’s Q3 results. Many articles note that all three companies’ stock prices fell after earnings announcements. The common reason appears to be concerns that memory shortages will cloud future performance outlooks. Since none of these companies are memory manufacturers, this suggests that memory shortages have become a shared challenge across the entire industry this year.

February 6, 2026

It appears that Intel and AMD have informed customers that shipments of CPUs to China will be delayed. Intel’s lead time is reportedly about six months, while AMD’s is expected to be up to ten weeks (approximately 2.5 months). The Intel CPUs in question are Xeon 4 (Sapphire Rapids) and Xeon 5 (Emerald Rapids), and the article reports that a large backlog of purchase orders has accumulated. Both Xeon 4 and Xeon 5 are manufactured on Intel 7.
There is also an article suggesting that NVIDIA may not release a gaming-oriented RTX-50 SUPER this year. It was reportedly planned to be announced at CES 2026, but the announcement has been postponed to December. The reason given is a potential shortage of LPDDR7. There is also speculation that the market launch of Rubin-based RTX-6000 series products may be delayed.
Another piece of NVIDIA-related news is that the location of its Taiwan headquarters land appears to have been decided in Taipei City.
Demand for AI semiconductors has led to a shortage of memory, with the impact spreading to CPUs and GPUs. There are forecasts suggesting that in 2026, data centers will absorb as much as 70% of total memory supply. Some articles note that if all three—memory, CPUs, and GPUs—are in short supply, servers themselves will become the subject of fierce competition. Traditionally, there has been a large gap between the pace of improvement in memory transfer speeds and CPU data processing speeds, a phenomenon known as the “memory wall.” If, however, the gap between market demand and semiconductor supply causes performance across the entire computer-related industry to decline, this might be considered a different kind of “memory wall.”
Mini news: A Windows 11 security patch reportedly reduces the frame rate of NVIDIA GeForce GPUs.

January 2026 Security Patch (KB5074109) (26200.7623)

February 7, 2026

It seems MediaTek has also released its earnings results. In its forward outlook, the company reportedly reached an agreement with TSMC to adopt both the 2nm and A14 (1.4nm) process nodes. While 2nm has already entered mass production, A14 was announced around last spring at TSMC’s Technology Symposium. Adopting leading-edge processes suggests that MediaTek intends to aggressively enter the HPC market. It is believed that memory shortages will mainly pressure the low-end market, while the high-end market will be less affected.
As an alternative to CoWoS, panel-based packaging technologies for mounting multiple chips within a package are beginning to emerge. TSMC refers to replacing CoWoS wafers with panels as CoPoS, while companies other than TSMC—such as ASE, SPIL, and SEMCO—are reportedly working on FOPLP (Fan-Out Panel-Level Packaging), which replaces wafers in FOWLP with panels. This appears to be an attempt to challenge CoWoS (and TSMC).
Speaking of packaging, TSMC has announced plans to build a 3nm production line in Kumamoto, Japan, but how packaging will be handled may be a challenge. There is reportedly a TSMC 3DIC R&D center in Tsukuba, but it does not seem intended for mass production. The TSMC Arizona fab is expected to add packaging facilities in the future. Rapidus has stated that it plans to handle packaging in-house as well (I recall seeing its president promoting a 600mm panel on television). Even if 3nm wafers are produced in Kumamoto, will they need to be shipped back to Taiwan? This may be an issue going forward.
In a somewhat unusual story, an article reported that an AMD Ryzen Threadripper Pro 9995WX reached 5.325GHz via overclocking with a custom water-cooled heatsink, consuming 1300W. The Ryzen 9995WX is based on Zen 5 (TSMC 4nm). The CPU was likely delidded and attached directly to the die. The water block design was reportedly unconventional, using S-shaped channels in the vertical plane rather than straight grooves, extending the flow path and improving cooling efficiency.
There was also an article suggesting that Qualcomm may use a cooling technology called Heat Pass Block (HPB) in the next Snapdragon generation. Details are unclear, but it may be applied to 2nm-generation chips. Another report states that Qualcomm’s India team has completed tape-out of a 2nm chip, though neither the chip details nor the specific fab were disclosed. If it is a Snapdragon, some speculate it may be taped out on Samsung’s 2nm process, but this remains uncertain.
Finally, an AWS topic: In its quarterly earnings, AWS reportedly announced plans to invest $200 billion in AI. Alphabet and Microsoft have also recently declared large AI investments. The total AI-related investment across these companies appears to be increasing year by year. Separately, several articles reported on intrusions into AWS environments using AI. Due to lax user-side security, environments were reportedly compromised in as little as eight minutes. Because AI does not hesitate to engage in trial-and-error like humans, once inside, lateral movement is said to be very fast.

Another AWS item: AWS and German power company RWE (Rheinisch-Westfälisches Elektrizitätswerk) reportedly signed a contract for the supply of 110MW of offshore wind power. AWS will provide cloud services to RWE, and RWE will supply electricity to AWS. A related article notes that Europe’s aging power transmission grid is slowing the deployment of high-voltage lines, delaying data center construction—by about two years compared to other regions. Google and Meta are reportedly facing similar issues. Even when discussing sovereign data centers or sovereign AI, whether facilities are actually located domestically makes a major difference. Accelerating grid upgrades appears necessary.

February 8, 2026 "Process Node" Status Quo (topic.2)

There was an article revealing internal details about NVIDIA’s $100 billion investment in OpenAI not going well. One background factor appears to be that OpenAI’s internally developed code-generation assistant (Codex) has underperformed, requiring inference capabilities beyond what NVIDIA GPUs alone can provide. As a result, OpenAI may be renting systems from companies such as Cerebras. Groq has also been mentioned as a candidate, and it is speculated that NVIDIA’s acquisition of Groq may be related to this situation. Since OpenAI is exploring multiple inference engines (possibly including AMD’s), this may be unappealing to NVIDIA. According to the article, this may be the real reason the investment is not proceeding smoothly.
Another NVIDIA-related note: NVIDIA reportedly allows its internal engineers to use a customized version of Anysphere Inc.’s code-generation AI, Cursor. The amount of generated code reportedly tripled, but since the bug rate did not improve with the initial deployment, NVIDIA customized the tool.

One more NVIDIA item: Samsung is reportedly set to begin mass production of HBM4 for Vera Rubin later this month.
Homework submission follows.

A few days ago, I wrote that “a 3-nm production line will be built at TSMC’s Kumamoto fab (FAB23), but ‘3 nm’ does not refer to the minimum circuit linewidth; since the 7-nm generation, the node name has effectively become just a trademark.” I would like to explain what this “minimum circuit linewidth” used to mean, and why today the numbers no longer match physical reality. To do that, it is first necessary to explain what “minimum circuit linewidth” actually signifies.

In semiconductor manufacturing, photomasks and exposure tools are used to fabricate LSIs by essentially making a reduced copy of a circuit pattern. When we make reduced photocopies in everyday life, if we reduce them too much, the characters blur and become unreadable. In the same way, in semiconductor fabrication, excessive scaling causes circuit formation to fail. Through various technical innovations, engineers push scaling to the very limit at which the circuit still functions without failure. The smallest wiring width that can be realized at this limit is what is called the minimum circuit linewidth.

Now, how do we shrink this minimum linewidth? When we hear about magnification or reduction, we might think of lenses, but in the semiconductor world the history is really about shortening the wavelength of the light source used in lithography tools. In process nodes such as 0.25 μm in the 1990s or 90 nm in the 2000s, light sources with wavelengths of 248 nm (KrF lasers) or 193 nm (ArF lasers) were used. From the 65-nm generation onward, 193-nm laser light was passed through water (ArF immersion), effectively achieving an equivalent wavelength of about 134 nm. A natural question is how it is possible to create patterns finer than the wavelength itself. This is achieved through optical correction techniques applied when printing wiring patterns. Even photomasks that look unintelligible at first glance can, when illuminated with monochromatic laser light, produce the intended wiring dimensions. To further increase wiring density, techniques such as multiple patterning—using several masks for the same layer—have been adopted, making photomask design CAD tools extremely complex.

With this historical background, from the 65-nm generation through the 16-nm, 14-nm, and 10-nm generations, process nodes (≈ minimum circuit linewidths) advanced using the same 134-nm-equivalent light source. This corresponds to the period when Intel manufactured Skylake (2015) on its 14-nm process, and when TSMC produced the iPhone X (2017) using its 10-nm process. After that, Intel struggled with its 10-nm process and did not produce Ice Lake until 2019. It is fair to say that this period marked the practical limit of ArF immersion lithography. TSMC, meanwhile, moved to the 7-nm generation and began introducing EUV lithography. EUV uses a wavelength of 13.5 nm—an order of magnitude shorter. (Terms such as “generation,” “process,” and “node” appear frequently here; note that they are used with roughly the same meaning.)

At this point some speculation is involved, but EUV has relatively low throughput, which likely made techniques such as multiple patterning difficult to use. That, in turn, would make it harder to form patterns much finer than the wavelength or to dramatically increase wiring density. From here on, the meaning of “scaling” the minimum circuit linewidth (≈ process node) begins to change.

By the 10-nm and 7-nm generations, both Intel and TSMC had transitioned to FinFETs, also known as tri-gate structures. In planar transistors before FinFETs, increasing transistor width (and thus drive current) required elongating the gate laterally, increasing area. With FinFETs, however, width can be gained in the vertical direction by increasing fin height, allowing the occupied area to be reduced. It is like moving from single-story houses to apartment buildings: the same number of households can live on a smaller plot of land. If the spacing between fins can also be reduced, area savings become even greater—like densely packed apartment complexes. The same applies to gate-all-around (GAA) FETs, such as TSMC’s nanosheet transistors at 2 nm and beyond, or Intel’s RibbonFETs at 18A and beyond.

Advancing a semiconductor process node carries several expectations, the most important being that LSIs become smaller. For the same circuit, a smaller area means more chips per wafer and therefore lower cost. Alternatively, for the same die area, more circuitry can be integrated, yielding higher performance at the same cost. Consequently, even if the minimum circuit linewidth itself does not shrink, advancing the process node still makes sense as long as more circuitry can be packed in. In this way, starting with the FinFET + EUV generations, the minimum circuit linewidth has effectively remained unchanged while the process node name has continued to advance as a branding concept.

So how can we tell the minimum circuit linewidth for each process node? Semiconductor manufacturers generally refer to industry roadmaps as benchmarks, though there is no strict obligation to follow them. About ten years ago, this roadmap was called the ITRS; today it is known as the IRDS. The IRDS covers the entire semiconductor industry, and within it the lithography section presents roadmaps for transistor structures and minimum circuit linewidths.

In the lithography roadmap, there are two definitions related to minimum linewidth. One is the minimum pitch of simple wiring—the distance from the center of one wire to the next, including the gap in between. Since wiring is metal, this is denoted as Mxx. The other is the contacted gate pitch, which represents transistor density. This pitch is defined as the distance between the centers of adjacent gates, including the source/drain contact next to the gate. More precisely, it is gate–space–contact–space–gate, measured from gate center to gate center. Because it is a gate pitch, it is denoted as Gxx. The GxxMxx notation I mentioned a few days ago comes directly from these roadmap values.

For reference, in the 2024 edition of the lithography roadmap, the values are G48M24 for the 3-nm node in 2024, G48M22 for the 2-nm node in 2025, and G48M22 again for the 1.4-nm node in 2027. Since this is a roadmap, these are projections and should be treated as such. Interpreting the numbers as explained above, G48 means the combined value of gate + space + contact + space. Dividing by four gives approximately 12 nm each for the gate, spaces, and contact. Similarly, M22 represents wire + space, so dividing by two yields about 11 nm each for the wire and the space. Considering that the EUV wavelength is 13.5 nm, it is reasonable to think that both gate and wiring minimum widths are on the order of about 12 nm.

According to the roadmap trend, from the 3-nm node to the 2-nm node, the gate pitch (G) remains unchanged while the metal pitch (M) shrinks by 2 nm. From the 2-nm node to the 1.4-nm node, both G and M are unchanged. There is no definitive proof that TSMC or Intel strictly adhere to these values, but they are reasonable reference dimensions. While more circuitry does fit as process nodes advance, the pace is no longer such that each generation doubles transistor count, as in the classic interpretation of Moore’s law. When people say that Moore’s law has slowed down, they are referring to exactly this situation.

In conclusion, to reiterate, advancing the process node today increases circuit density through means other than shrinking the minimum circuit linewidth. While this poses no industrial problem, the “xx-nm generation” indicated by the process node has diverged from the actual minimum wiring width. As an aside, the lattice constant of silicon is 5.431 angstroms. A “14A” process node literally means 14 angstroms, and future roadmaps go below 10A to 7A and 5A. Demand for AI semiconductors is pushing nodes forward, and with transistor structures evolving toward CFETs, scaling efficiency is expected to improve. If, when we reach the 5A node, someone says, “Isn’t something strange here?”, I hope this explanation will come to mind.

That was a long explanation, but that is all I wanted to convey. I think it is a wonderful development that a 3-nm-generation manufacturing line will be built at TSMC’s Kumamoto fab.

February 9, 2026

It seems TSMC held a board meeting in Kumamoto, likely related to the 3nm line construction. After Chairman C.C. Wei reportedly made a request to Japan’s prime minister, the board may have approved it. If so, holding the meeting in Kumamoto makes sense. Incidentally, TSMC held a board meeting in Arizona last year.
Two Intel-related topics have emerged. One concerns chipset information for the next-generation Intel Core Ultra Series 4 (Nova Lake). The 9xx series chipsets begin with Z/B/Q/W, with Z990 as the high end. These are expected to reach the market around the Christmas shopping season this year.
The other is that Intel’s “Intel On Demand” service has reportedly ended unofficially (with no formal announcement). Intel CPU spec sheets list many features, but users must pay separately to enable some of them. Initially this was called SDSi (Software Defined Silicon). This includes SGX (Software Guard Extensions), which provides device-rooted information protection. “In Device We Trust” will likely grow in importance, and it remains to be seen whether such features will be enabled by default in future CPUs.
In data center news, Murata Manufacturing reportedly used 5th-generation AMD EPYC processors to triple simulation throughput while reducing workload power consumption to one-third. These were likely Zen 5 (Turin, 4nm) CPUs. Zen 5c (3nm) has smaller memory capacity and may be less suitable for simulations. While the baseline system is unclear, lower voltage, more cores, and larger cache typically reduce power and increase throughput—an example of scaling benefits.
Numerous articles report that AWS partnered with STMicroelectronics. ST will supply microcontrollers and communication chips for AWS data centers and is also co-developing chips with AWS.
Another data center note: MC Digital Realty’s NRT14 data center in Inzai (Chiba Prefecture) reportedly became the first in Japan to receive NVIDIA certification for liquid-cooled DGX systems, enabling GB200 NVL72 racks. “NRT” is derived from Narita Airport’s IATA code.

February 10, 2026

There are reports that MediaTek may adopt Intel’s 14A process. Other articles recently noted access to TSMC’s 2nm and A14. Since “A14” and “14A” sound similar—and “14A” could also be read as angstroms—confusion is possible.
Related to Intel’s 14A, backside power delivery (BSPD) is reportedly set to become standard from 18A onward. TSMC is expected to offer it as an option, possibly from N2P or A16. BSPD faces several challenges. One is self-heating: thinning the silicon layer increases thermal resistance, making it harder for heat to dissipate from both signal (front) and power (back) sides, causing junction temperatures to rise. Backside power routing will require simultaneous electrical and thermal design. The necessary simulation tools likely already exist; what remains is execution.
Another challenge lies in LSI design methodology. With separated signal and power layers, new design and verification environments are needed. Signal routing cannot simply be tightened due to crosstalk concerns, and timing analysis, designer intuition, and reuse from previous generations make technology migration difficult. This may be the larger issue. TSMC works closely with EDA vendors such as Synopsys, Cadence, and Siemens—how Intel handles this is less clear. Rapidus in Japan has stated it will support BSPD relatively early.

Another Intel note: The upcoming desktop CPU Nova Lake-S may reach a maximum power consumption of 700W when all 52 cores are fully active. Not long ago, that was the power rating of an entire mid-tower PC.
In a less common area, Cisco released the Silicon One G300 network chip, manufactured on TSMC’s 3nm process, competing with Broadcom’s Tomahawk. Network paths often become bottlenecks in AI computing, and rerouting can improve performance. Silicon One G300 reportedly improves some AI workloads by 28%.
ARM Holdings’ recent earnings showed strong royalty income due to AI-driven chip sales, though licensing revenue was lower than expected. Licensing fees are paid during chip development, while royalties are paid after chip sales. While memory shortages may reduce chip sales in 2026, licensing revenue provides some offset.
In cloud news, Google reported an astonishing 48% growth in Q4. While Google’s revenue base is smaller than Microsoft’s or AWS’s, 48% represents roughly 1.5× growth, likely driven by Gemini 3. AWS reportedly surpassed Microsoft in Q4 revenue. Cloud business remains strong overall.

February 11, 2026

It appears that MediaTek has won the ASIC development contract for Google’s TPU v8e. Up through TPU v7p, Broadcom handled the work, although MediaTek reportedly took charge of the I/O portion for v7p. This time, it seems MediaTek may have been awarded the entire design. An article suggests that SerDes performance was the deciding factor. For AI chips, communication bandwidth appears to be critical.
Continuing with Google-related news, there was an article stating that Intel and Google jointly validated Intel TDX (Trust Domain Extension), identified vulnerabilities and bugs, and implemented countermeasures. TDX was introduced after SGX, and while both are security-related features, SGX operates at the application level, whereas TDX provides security at the VM level. Trust in the device itself (root of trust) is becoming increasingly important. AMD has SEV, and Arm has CCA. Cloud service providers (CSPs) such as Google and Microsoft (Azure) provide a device-rooted chain of trust.
Another Intel-related topic: Toward the end of January, there was speculation that Intel Foundry would be used for the I/O chip of NVIDIA’s next-generation GPU, Feynman. New articles suggest that Intel may also be used for packaging. TSMC will still be involved, with an estimated split of roughly 75% TSMC and 25% Intel.
Continuing with NVIDIA news, I wrote last week that NVIDIA’s Taiwan headquarters was likely to be located in Taipei. It now appears that the contract has been officially signed. The lease term is 50 years, with an option to extend by up to 20 years. Starting from 2026, this would run as long as 2096.
Switching topics, regarding so-called “Trump tariffs” in Taiwan: In the semiconductor sector, it has been reported that U.S. suppliers designated by TSMC will be exempt from import tariffs. In other words, hyperscalers such as Google, AWS, and Microsoft will purchase large volumes of chips from TSMC, and if TSMC designates them as exempt vendors, U.S. tariffs on imports from Taiwan will be waived. This is reportedly based on legislation allowing Taiwanese semiconductor companies that have already invested in U.S. facilities to import chips duty-free up to 1.5 times their investment amount, or up to 2.5 times for new investments. Semiconductor companies can choose which customers receive the exemption. TSMC has made massive investments in the U.S. and plans to build around six fabs, and this appears to have paid off.
Finally, some news from Japan. There was an article stating that Fujitsu will begin domestic manufacturing of AI servers. The factory is reportedly located in Ishikawa Prefecture, likely operated by Fujitsu IT Products. Neither company has released a formal press announcement yet. Fujitsu’s server products, as well as the K and Fugaku supercomputers, were manufactured there. The stated goal is to prevent information leakage, suggesting the importance of domestic production. However, it is not entirely clear what is meant by “AI servers.” Are these IA (x86) servers, or could they be servers based on FUJITSU-MONAKA (TSMC 2nm), which Fujitsu is currently developing as a data-center CPU? Further details are awaited.
Mini news: In Windows 11’s semiannual update cycle, the upcoming release believed to be 26H1 will reportedly support only Arm CPUs and will not be an update to 25H2.

February 12, 2026

It appears that the NPU 6 integrated into Intel’s Nova Lake will deliver 74 TOPS of performance. By comparison, Panther Lake’s NPU 5 offers 50 TOPS, making Nova Lake about 1.5× faster. NPU 4, used in Lunar Lake, delivers 48 TOPS, while NPU 3 in Arrow Lake provides about 13 TOPS. Panther Lake was announced at CES in January, but it appears there will be no desktop version. Lunar Lake is also notebook-only, so for the first half of 2026, a refreshed Arrow Lake is expected for desktops, reportedly still with a 13 TOPS NPU. With Nova Lake arriving toward year-end, the NPU performance gap will be about 5.7×. Since Windows + Copilot is said to require 40 TOPS, those considering an AI PC may want to think carefully before choosing Arrow Lake Refresh. (NPU 4 and NPU 5 reportedly have similar performance, but differ in area efficiency.)
Another Intel-related item: Tower Semiconductor of Israel had planned to manufacture silicon photonics devices at Intel’s Fab 11X in New Mexico, but this plan has reportedly been canceled. Instead, Tower Semiconductor will carry out production in Japan, at a facility in Toyama (TPSCo Fab 7). Silicon photonics is expected to see growing demand for AI data centers.
Samsung has reportedly begun mass shipments of HBM4, marking its first deliveries to NVIDIA. SK hynix shipped samples earlier, but mass production shipments have not yet begun.
Another Samsung note: The next-generation smartphone CPU, Exynos 2600 (Samsung 2nm), will reportedly support Arm’s SME2. The competing Qualcomm Snapdragon 8 Elite Gen 5 is believed to support SME.
NVIDIA’s RTX 6000 PRO GPU is equipped with 96GB of GDDR7, but in China there is reportedly an RTX 6000D variant with 84GB. Since each GDDR7 chip is 3GB, this corresponds to 32 chips versus 28 chips. The 6000D also reportedly has a narrower bus and fewer shaders. Both are based on the Blackwell architecture. While it was unclear whether China imported the previous-generation H200, the fact that current Blackwell-based products are already available may be because they use GDDR rather than HBM. In other words, NVIDIA may have designed these products from the outset to be exportable to China.
Turning to AMD: According to a research firm, AMD’s revenue share in the overall server market exceeded 40% in Q4 2025, reaching 41.3%. It was 39.5% in Q3, so this may have been only a matter of time. AMD’s server CPU unit share stands at 28.8%, nearly 30%. In the desktop segment, AMD’s revenue share reached 42.6%, also exceeding 40%, with a CPU unit share of 36.4%. In both servers and desktops, AMD now accounts for roughly 40% of industry revenue.
In Japan-related news, Rapidus is reportedly planning monthly wafer production of 6,000 wafers in 2027, increasing to 25,000 wafers per month in 2028, and eventually to 60,000 wafers per month. Since 2026 is the year when 2nm-generation products enter the market, this seems to mark the real start. After 40nm, the number of fabs steadily declined, but at 2nm, Rapidus has joined TSMC, Intel, and Samsung. At the same time, AI semiconductor demand is surging, suggesting favorable conditions.
Regarding Fujitsu’s domestic server manufacturing mentioned yesterday, a press release now appears to have been issued, and domestic coverage has increased. The article I saw yesterday was from Nikkei Asia, so it may have been early. The “AI servers” turn out to be both servers based on FUJITSU-MONAKA and GPU servers using NVIDIA B300 and RTX 6000 PRO. FUJITSU-MONAKA adopts the Arm architecture, like Fugaku’s A64FX (TSMC 7nm).

February 13, 2026

I recall reading an article in mid-January that OpenAI had adopted Cerebras’s WSE, and now there is news that OpenAI has built its Codex model (GPT-5.3-Codex-Spark) on Cerebras. This is reportedly the first OpenAI model to run on non-NVIDIA hardware. Code generation speed is said to be 1,000 tokens per second (TPS). For comparison, Anthropic’s Claude Opus 4.6 was listed at 68.2 TPS. Other examples of models running on Cerebras include Meta’s Llama 3.1 70B at 2,100 TPS and OpenAI’s gpt-oss-120B at 3,000 TPS. Judging by these numbers, Codex may be a relatively heavy model, while at the same time highlighting the impressive capability of Cerebras. As a wafer-scale engine (WSE), it reinforces the idea that, for AI chips, size is performance.
There has been attention on comments by AWS CEO Matt Garman regarding the impact of generative AI on the software industry. Concerns have been raised that powerful code generation could make software development companies unnecessary or signal the end of SaaS, and SaaS-related stocks such as Salesforce have reportedly been weak. Posts on X also suggest that software houses are being cornered. Garman’s remarks appear to argue that these fears are exaggerated. At a recent Cisco AI Summit, NVIDIA’s Jensen Huang also stated that the outlook for the software industry is bright. The industry may currently be in a somewhat hysterical state. While generative AI may indeed encourage a shift from SaaS to in-house (on-prem) development and more personal coding, it is hard to imagine cloud services declining. Rather, as a platform, the cloud is likely to continue expanding alongside global population growth, and demand for software development is probably just getting started. When PCs emerged in the 1980s, there was talk of a “software crisis,” yet software engineers have remained in short supply ever since, partly because programming languages are difficult. It may be more accurate to say that the true value of software development expertise is only now coming into its own.
Another AWS-related item: There was an article stating that AWS will lead the construction of a data center in Washington State. It is reportedly located near a port and has a power contract with a nuclear plant. Although unconfirmed, it may be near a submarine cable landing point.
A bit of LSI-related news: I recall an article late last month suggesting that Apple’s base M5 might be manufactured by Intel, and now there are reports that the M5 Pro and Max may adopt TSMC’s SoIC packaging technology, separating CPU and GPU into chiplets. Recently, even large GPUs have begun separating I/O into chiplets, and most XPUs may now be chiplet-based. The article cited Qualcomm’s Snapdragon X2 Elite as an example that has not yet adopted chiplets.
A somewhat unusual topic: Japan’s PayPay is reportedly planning to list on Nasdaq in New York. It is said to be preparing for an IPO. Preparations began last year, but delays due to government shutdowns caused by budget shortfalls reportedly pushed the timeline to now. The ticker symbol will be PAYP.

February 14, 2026 Break the Curse of Software (topic.2)

It appears that Intel has discontinued Intel Quantum Passes, which were included in the Intel Quantum SDK. I do not fully understand the details, but originally, quantum programs would be compiled and executed on quantum chips such as Tunnel Falls. When using quantum simulators based on HPC systems or GPUs instead of actual quantum computers, programs must be compiled specifically for those simulators. Quantum Passes seem to have served as a bridge between quantum compilation and simulator-specific compilation. Intel has developed a quantum chip called Tunnel Falls and has provided it to research institutions; I recall reading an article in mid-January about its delivery to Argonne National Laboratory. Recently, Intel On Demand (formerly SDSi), which allowed users to purchase additional CPU features, appears to have been unofficially discontinued, and Intel’s open-source initiatives seem to be winding down.
Intel’s 52-core Nova Lake-S is rumored to reach 700W when power limits are removed. The core configuration is reportedly 16 P-cores (Coyote Cove, Intel 18A) with 16 threads, 32 E-cores with 32 threads, and 4 LP-E cores with 4 threads—all single-threaded per core. Up through the first-generation Core Ultra (Meteor Lake), P-cores supported two threads (Redwood Cove, Intel 4), but from the second generation onward, P-cores are single-threaded.
Yesterday I wrote that OpenAI achieved 1,000 TPS by running Codex on Cerebras’s WSE-3. A throughput of 1,000 TPS is said to correspond to human-level pair-programming responsiveness. Extending this idea, if AI can drive coding, could development timelines for software stacks—compilers, drivers, OS integration, databases, VMs, and porting existing applications—be shortened by analyzing processor architecture specifications? In other words, while it takes months to fabricate an LSI, if the architecture specification and RTL netlist exist as a “paper machine,” could at least a prototype software stack be ready by the time the chip arrives? Of course, it is not that simple, but today both CPUs and GPUs have relatively few architectural variants. If AI coding becomes widespread, it may influence processor design itself. Intel has tried several times to abandon x86 but was ultimately pulled back by its software legacy. Japan’s supercomputers moved from SPARC64 in the K system to Arm in Fugaku partly to broaden the software ecosystem. Perhaps AI coding will one day free architectures from software constraints—this thought occurred to me.
There was also an article about the launch of the Trusted Tech Alliance (TTA) at the Munich Security Conference, involving 15 companies from 10 countries. The founding members include Anthropic, AWS, Cohere, Ericsson, Google Cloud, Microsoft, Nokia, NTT, Rapidus, SAP, and six others, spanning AI, cloud, communications, semiconductors, and databases—the core industries of today’s digital society. The alliance aims to expand gradually. In a digital society where information spreads instantly worldwide, there are many benefits, but attackers can also strike from safe havens. For those without malicious intent, trust becomes essential for connectivity.
A bit more Japan-related news: NTT Data, a subsidiary of NTT and a TTA member, has reportedly signed a multi-year contract with AWS and acquired Dubai-based Zero&One, an AWS-certified partner. In another item, Fujitsu is set to give presentations and exhibitions at the India AI Impact Summit 2026, to be held next week. This is the event where many articles reported that NVIDIA’s Jensen Huang would be absent. Fujitsu will reportedly showcase quantum computing, FUJITSU-MONAKA, and demonstrations of its Japanese-language LLM, Takane. Takane is also being co-developed with Cohere, another TTA member.
ISSCC 2026 begins tomorrow. The plenary session on the 16th will feature four talks from MediaTek, IBM, Cadence, and Apple.

This Blog text was translated by AI from Japanese Source Blog.

(to be continued to 2nd Half of Feb.)

Saturday, February 14, 2026

FEB.(1st Half) 2026